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PSMN4R0-25YLC 数据表(PDF) 6 Page - NXP Semiconductors

部件名 PSMN4R0-25YLC
功能描述  N-channel 25 V 4.5 m logic level MOSFET in LFPAK
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PSMN4R0-25YLC 数据表(HTML) 6 Page - NXP Semiconductors

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PSMN4R0-25YLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 2 December 2010
6 of 15
NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 m
Ω logic level MOSFET in LFPAK
6.
Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID =250 µA; VGS =0V; Tj = 25 °C
25
--V
ID =250 µA; VGS =0V; Tj = -55 °C
22.5
-
-
V
VGS(th)
gate-source threshold
voltage
ID =1mA; VDS =VGS; Tj =25°C;
see Figure 10
1.05
1.53
1.95
V
ID =10mA; VDS =VGS; Tj =150 °C;
see Figure 11
0.5
--V
VGS(th)
gate-source threshold
voltage
ID =1mA; VDS =VGS; Tj =-55 °C;
see Figure 11
--2.25
V
IDSS
drain leakage current
VDS =25V; VGS =0V; Tj = 25 °C
--1
µA
VDS =25V; VGS =0V; Tj = 150 °C
-
-
100
µA
IGSS
gate leakage current
VGS =16V; VDS =0V; Tj = 25 °C
-
-
100
nA
VGS =-16 V; VDS =0V; Tj = 25 °C
-
-
100
nA
RDSon
drain-source on-state
resistance
VGS =4.5 V; ID =20A; Tj =25°C;
see Figure 12
-4.5
5.8
m
VGS =4.5 V; ID =20A; Tj =150 °C;
see Figure 12; see Figure 13
--9.85
m
VGS =10V; ID =20A; Tj =25°C;
see Figure 12
-3.5
4.5
m
VGS =10V; ID =20A; Tj = 150 °C;
see Figure 12; see Figure 13
--7.65
m
RG
internal gate resistance
(AC)
f=1MHz
-
2.1
4.2
Dynamic characteristics
QG(tot)
total gate charge
ID =20A; VDS =12V; VGS =10V;
see Figure 14; see Figure 15
-
22.8
-
nC
ID =0A; VDS =0V; VGS =10V;
see Figure 14
-
21.1
-
nC
ID =20A; VDS =12V; VGS =4.5 V;
see Figure 14; see Figure 15
-
10.9
-
nC
QGS
gate-source charge
-
3.3
-
nC
QGS(th)
pre-threshold
gate-source charge
-2.25
-nC
QGS(th-pl)
post-threshold
gate-source charge
-1.05
-nC
QGD
gate-drain charge
ID =20A; VDS 12 V; VGS =4.5 V;
see Figure 14; see Figure 15
-3.5
-nC
VGS(pl)
gate-source plateau
voltage
VDS =12V; see Figure 14;
see Figure 15
-2.58
-V
Ciss
input capacitance
VDS =12V; VGS = 0 V; f = 1 MHz;
Tj =25°C; see Figure 16
-
1407
-
pF
Coss
output capacitance
-
354
-
pF
Crss
reverse transfer
capacitance
-119
-pF


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