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DAC34H84 数据表(PDF) 11 Page - Texas Instruments |
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DAC34H84 数据表(HTML) 11 Page - Texas Instruments |
11 / 96 page DAC34H84 www.ti.com SLAS751D – MARCH 2011 – REVISED SEPTEMBER 2015 6.7 Electrical Characteristics – AC Specifications over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT(1) PLL OFF 1250 fDAC Maximum DAC rate MSPS PLL ON 1000 AC PERFORMANCE(2) fDAC = 1.25 GSPS, fOUT = 20 MHz 73 Spurious free dynamic range SFDR fDAC = 1.25 GSPS, fOUT = 50 MHz 70 dBc (0 to fDAC/2) Tone at 0 dBFS fDAC = 1.25 GSPS, fOUT = 70 MHz 66 fDAC = 1.25 MSPS, fOUT = 30 ± 0.5 MHz 87 Third-order two-tone intermodulation distortion IMD3 fDAC = 1.25 GSPS, fOUT = 50 ± 0.5 MHz 85 dBc Each tone at –12 dBFS fDAC = 1.25 GSPS, fOUT = 100 ± 0.5 MHz 78 fDAC = 1.25 GSPS, fOUT = 10 MHz 160 Noise Spectral Density(3) NSD dBc/Hz Tone at 0dBFS fDAC = 1.25 GSPS, fOUT = 80 MHz 155 fDAC = 1.2288 GSPS, fOUT = 30.72 MHz 77 Adjacent channel leakage ratio, single carrier fDAC = 1.2288 GSPS, fOUT = 153.6 MHz 74 ACLR(3) dBc fDAC = 1.2288 GSPS, fOUT = 30.72 MHz 82 Alternate channel leakage ratio, single carrier fDAC = 1.2288 GSPS, fOUT = 153.6 MHz 80 Channel Isolation fDAC = 1.25 GSPS, fOUT = 10 MHz 95 dBc (1) Measured single ended into 50 Ω load. (2) 4:1 transformer output termination, 50 Ω doubly terminated load (3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms 6.8 Timing Requirements – Digital Specifications MIN NOM MAX UNIT CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% DACCLKP/N input frequency 1250 MHz OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive fDACCLK / fOSTR Frequency MHz integer, fDACCLK is DACCLK frequency in MHz (8 x interp) Duty cycle 50% DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching Config36 Setting datadly clkdly 0 0 150 0 1 100 0 2 50 0 3 0 Setup time, 0 4 -50 DAB[15:0]P/N, DCD[15:0]P/N, 0 5 -100 ISTRP/N, ISTRP/N and SYNCP/N reset latched ts(DATA) 0 6 -150 SYNCP/N and only on rising edge of DATACLKP/N 0 7 -200 ps PARITYP/N, valid to either edge of 1 0 200 DATACLKP/N 2 0 250 3 0 300 4 0 350 5 0 400 6 0 450 7 0 500 Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC34H84 |
类似零件编号 - DAC34H84_15 |
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类似说明 - DAC34H84_15 |
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