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UC1856-SP 数据表(PDF) 5 Page - Texas Instruments |
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UC1856-SP 数据表(HTML) 5 Page - Texas Instruments |
5 / 23 page COMP CS CS V G ; V 0 to 1 V V D = D - = D + UC1856-SP www.ti.com SLUSBV6 – APRIL 2014 6.5 Electrical Characteristics Unless otherwise stated, these specifications apply for TA –55°C to +125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE SECTION Output voltage TJ = 25°C, lO = 1 mA 5.05 5.1 5.15 V Line regulation VIN = 8 to 40 V 20 mV Load regulation lO = –1 mA to –10 mA 15 mV Total output variation Line, load, and temperature 5 5.2 V Output noise voltage 10 Hz < f < 10 kHz, TJ = 25°C 50 µV Long-term stability TJ = 125°C, 1000 Hrs (1) 5 25 mV Short-circuit current VREF = 0 V –25 –45 –65 mA OSCILLATOR SECTION TJ = 25°C 180 200 220 Initial accuracy kHz Over operating range 170 230 Voltage stability VIN = 8 to 40 V 2% TJ = 25°C, VCT = 2 V 7.5 8 8.8 Discharge current mA Over operating range, VCT = 2 V 6.7 8 8.8 Sync output high level lO = –1 mA 2.4 3.6 V Sync output low level lO = 1 mA 0.2 0.4 V Sync input high level CT = 0 V, RT = VREF 2 1.5 V Sync input low level CT = 0 V, RT = VREF 1.5 0.8 V Sync input current CT = 0 V, RT = VREF, VSYNC = 5 V 1 10 µA Sync delay to outputs CT = 0 V, RT = VREF, VSYNC = 0.8 to 2 V 50 100 ns ERROR AMPLIFIER SECTION Input offset voltage VCM = 2 V 5 mV Input bias current –1 µA Input offset current 500 nA Common mode range VIN = 8 V to 40 V 0 VIN-2 V Open loop gain VO = 1.2 V to 3 V 80 100 dB Unity gain bandwidth TJ = 25°C 1 1.5 MHz CMRR VCM = 0 V to 38 V, VIN = 40 V 75 100 dB PSRR VIN = 8 V to 40 V 80 100 dB Output sink current VID = –15 mV, VCOMP = 1.2 V 5 10 mA Output source current VID = 15 mV, VCOMP = 2.5 V –0.4 –0.5 mA Output high level VID = 50 mV, RL (COMP) = 15 kΩ 4.3 4.6 4.9 V Output low level VID = –50 mV, RL (COMP) = 15 kΩ 0.7 1 V CURRENT SENSE AMPLIFIER SECTION Amplifier gain VCS– = 0 V, CL SS Open (2) (3) 2.5 2.75 3 V/V Maximum differential-input signal CL SS Open(2), RL (COMP) = 15 kΩ 1.1 1.2 V (VCS+ – VCS–) Input offset voltage VCL SS = 0.5 V, COMP Open (3) 5 35 mV CMRR VCM = 0 V to 3 V 60 dB PSRR VIN = 8 V to 40 V 60 dB Input bias current VCL SS = 0.5 V, COMP Open (2) –1 1 µA Input offset current VCL SS = 0.5 V, COMP Open (2) –1 1 µA Input common-mode range 0 3 V VEA+ = VREF, EA– = 0 V Delay to outputs 120 250 ns CS+ – CS– = 0 V to 1.5 V (1) This parameter, although ensured over the recommended operating conditions, is not 100% tested in production. (2) Parameter measured at trip point of latch with VEA+ = VREF, VEA– = 0 V. (3) Amplifier gain defined as: Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: UC1856-SP |
类似零件编号 - UC1856-SP_15 |
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类似说明 - UC1856-SP_15 |
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