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UC1825-SP 数据表(PDF) 9 Page - Texas Instruments |
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UC1825-SP 数据表(HTML) 9 Page - Texas Instruments |
9 / 18 page 4 5 6 4 16 6 UC1825 Clock RT CT Master RT 5 UC1825 Slave Clock VREF RT CT Local Ramp CT Two Units in Close Proximity 16 4 5 6 UC1825 VREF Clock RT CT Local Ramp Master 10 mF 2N222 RT CT 43 W 0.1 mF 43 W 0.1 mF To Other Slaves 24 W 24 W CT 5 6 UC1825 Slave Local Ramp CT RT 1.5 W RT CT 5 6 RT 43 W 0.1 mF 43 W 0.1 mF 470 W Generalized Synchronization RFF CFF 7 UC1825 RT VIN 16 5 6 Ramp Clock CT VIN RR 9 14 11 ILIM Shut- Down UC1825 Out B Out A CR UC1825-SP www.ti.com SLUS870A – JANUARY 2009 – REVISED MARCH 2012 Figure 5. Synchronized Operation Figure 6. Forward Technique for Off-Line Voltage Mode Application The circuit shown in Figure 6 will achieve a constant volt-second product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at the ILIM/SD pin crosses the 1-V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum deadtime. Figure 7. Constant Volt-Second Clamp Circuit Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): UC1825-SP |
类似零件编号 - UC1825-SP |
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类似说明 - UC1825-SP |
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