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74LVC373A 数据表(PDF) 10 Page - NXP Semiconductors |
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74LVC373A 数据表(HTML) 10 Page - NXP Semiconductors |
10 / 19 page 74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 3 — 22 November 2012 10 of 19 NXP Semiconductors 74LVC373A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. 3-state enable and disable times mna886 tPLZ tPHZ output disabled output enabled VY VX output enabled Qn output LOW-to-OFF OFF-to-LOW Qn output HIGH-to-OFF OFF-to-HIGH OE input VOL VOH VCC VI VM GND GND tPZL tPZH V M VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 11. Data set-up and hold times for the Dn input to the LE input mna887 th tsu th tsu VM VM VI GND VI GND LE input Dn input Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 V CC 0.5 V CC VOL + 0.15 V VOH 0.15 V 1.65 V to 1.95 V VCC 0.5 V CC 0.5 V CC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V VCC 0.5 V CC 0.5 V CC VOL + 0.15 V VOH 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V |
类似零件编号 - 74LVC373A_15 |
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类似说明 - 74LVC373A_15 |
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