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74AHC3GU04 数据表(PDF) 2 Page - NXP Semiconductors |
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74AHC3GU04 数据表(HTML) 2 Page - NXP Semiconductors |
2 / 16 page 74AHC3GU04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 8 May 2013 2 of 16 NXP Semiconductors 74AHC3GU04 Triple unbuffered inverter 4. Marking [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 6. Pinning information 6.1 Pinning Table 2. Marking codes Type number Marking code[1] 74AHC3GU04DP AU4 74AHC3GU04DC AU4 74AHC3GU04GD AU4 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) mna720 1A 1Y 17 2A 2Y 35 3A 3Y 62 7 1 1 1 5 3 mna721 1 2 6 mna045 AY Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8) 74AHC3GU04 1A VCC 3Y 1Y 2A 3A GND 2Y 001aaj517 1 2 3 4 6 5 8 7 001aaj518 74AHC3GU04 Transparent top view 8 7 6 5 1 2 3 4 1A 3Y 2A GND VCC 1Y 3A 2Y |
类似零件编号 - 74AHC3GU04_15 |
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类似说明 - 74AHC3GU04_15 |
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