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LTC2373-18 数据表(PDF) 18 Page - Linear Technology |
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LTC2373-18 数据表(HTML) 18 Page - Linear Technology |
18 / 50 page LTC2373-18 18 237318f For more information www.linear.com/LTC2373-18 applicaTions inForMaTion Figure 4. Equivalent Circuit for the Differential Analog Inputs of the LTC2373-18 ANALOG INPUTS The LTC2373-18 can be configured to accept one of three voltage ranges: fully differential (±4.096V), pseudo- differentialunipolar(0Vto4.096V),andpseudo-differential bipolar(±2.048V).Inallthreeranges,theADCsamplesand digitizes the voltage difference between the two ADC core analog input pins (ADCIN+ − ADCIN−), and any unwanted signal that is common to both inputs is reduced by the common mode rejection ratio (CMRR) of the ADC. The MUXoutputsthevoltagesoftheselectedMUXanaloginput channels to MUXOUT+/–, according to the MUX configu- ration. MUXOUT+/– may be wired directly to ADCIN+/– or connected through a buffer. Refer to the Configuring the LTC2373-18sectionfordetailsonhowtoselecttheanalog input range and MUX channel configuration. Independentoftheselectedrangeorchannelconfiguration, the MUX analog inputs can be modeled by the equivalent circuit shown in Figure 4. CHx and CHy are distinct input pins selected from the CH0 to CH7 MUX analog inputs, depending on the MUX configuration. Each pin has ESD protection diodes. The ADC core analog inputs, ADCIN+/–, each see a sampling network consisting of approximately 50pF (CIN) from the sampling CDAC in series with 40Ω (RON) from the on-resistance of the sampling switch. The MUX is modeled by a 40Ω resistor representing the MUX switch on-resistance (RSW) and a capacitance to ground, CPAR, at the output summing node of the MUX. CPAR is a lumped capacitance on the order of 20pF formed primarily by pin parasitics and diode junctions. Parasitic capacitances from the PCB will also contribute to CPAR. This capacitance is discharged through a switch to ground every conversion cycle or when a first new configuration is programmed to minimize crosstalk due to charge sharing between channels. During acquisition, each active MUX analog input sees a cascade of two first order lowpass filters formed by RSW, CPAR and the ADC sampling network when MUXOUT+/– is wired directly to ADCIN+/–. If a buffer is inserted between MUXOUT+/– and ADCIN+/–, then each active MUX analog input only sees a first order lowpass filter formed by RSW and CPAR that is loaded with the input impedance of the buffer. BothCINandCPARdrawcurrentspikeswhilebeingcharged during acquisition. If MUXOUT+/– is wired directly to ADCIN+/–, the current spikes from the charging of both capacitors are drawn from the active MUX analog inputs. A buffer inserted between MUXOUT+/– and ADCIN+/– will absorbthecurrentspikefromCIN,leavingthecurrentspike from CPAR to be drawn from the active MUX analog inputs. During conversion and sleep, the MUX analog inputs and ADC core analog inputs draw only a small leakage current. 237318 F04 VDD RON 40 CIN 50pF ADCIN+ OR VDD RON 40 CIN 50pF BIAS VOLTAGE ADCIN– MUXOUT+ MUXOUT– MUX ADC CORE OR VDD RSW 40 CPAR 20pF CHX VDD VDD RSW 40 CHY, COM CPAR 20pF VDD |
类似零件编号 - LTC2373-18_15 |
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类似说明 - LTC2373-18_15 |
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