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BU26154MUV 数据表(PDF) 3 Page - Rohm

部件名 BU26154MUV
功能描述  High PSRR is attained by built-in regulator
Download  89 Pages
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制造商  ROHM [Rohm]
网页  http://www.rohm.com
标志 ROHM - Rohm

BU26154MUV 数据表(HTML) 3 Page - Rohm

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TSZ02201-0V1V0R501570-1-2
© 2014 ROHM Co., Ltd. All rights reserved.
23.Jun.2014 Rev.001
www.rohm.com
TSZ22111 • 15 • 001
BU26154MUV
2
HPVDD
O
CPVDD
A positive side voltage output pin for the headphones
driver.
A capacitor is connected between HPVDD and CPGND.
Please connect as close as possible to the chip.
CPGND
(Note 2)
4
HPVSS
O
CPVDD
A negative side voltage output pin for the headphones
driver.
A capacitor is connected between HPVSS and CPGND.
Please connect as close as possible to the chip.
CPGND
(Note 2)
22
MCLKI
I
HVDD
Master Clock pin
(input)
HGND1
21
TSTO
O
HVDD
Output pin for test-mode.
Make it open.
HGND1
Open
20
RESETB
I
HVDD
Reset pin
"L" level: Reset enables.
"H" level: Reset disable.
(input)
-
24
SDATA
/SDA
IO
HVDD
3 wire interface: data input output pin
It is indicated as SDATA.
2 wire interface: data input output pin
(Note 1)
It is indicated as SDA.
(input)
-
25
SCLK
/SAD
I
HVDD
3 wire interface: Serial clock input pin
It is indicated as SCLK.
2 wire interface: Slave address select input pin.
It is indicated as SAD.
SAD pin = "L" level slave address is "0011010"
SAD pin = "H" level slave address is "0011011"
(input)
HGND1
23
CSB
/SCL
I
HVDD
3 wire interface: chip select input pin
It is indicated as CSB.
2 wire interface: Serial clock input pin *1
It is indicated as SCL.
(input)
-
26
SAI_LRCLK
IO
HVDD
SAI LR clock input/output pin
(input)
HGND1
27
SAI_BCLK
IO
HVDD
SAI bit clock input/output pin
(input)
HGND1
28
SAI_SDIN
I
HVDD
SAI serial data input pin
(input)
HGND1
29
SAI_SDOUT
O
HVDD
SAI serial data output pin
HGND1
Open
30
IRQB
O
HVDD
An interrupt output terminal. When an interrupt occurs,
chip outputs "L".
HGND1
Open
10
VMID
O
REGOUT
Analog reference voltage pin
A capacitor is connected between VMID and HGND2.
HGND2
-
11
MBIASCAP
O
HVDD
Microphone bias voltage output pin
A capacitor is connected between HGND2.
Please connect as close as possible to the chip.
HGND2
Open
12
MIN1
I
REGOUT
Analog microphone input 1
Single-end and differential can be chosen.
When differential is chosen, it connects with microphone
+ pin.
Hi-Z
Open
13
MIN2
I
REGOUT
Analog microphone input 2
Single-end and differential can be chosen.
When differential is chosen, it connects with microphone
- pin.
Hi-Z
Open
8
SPOUT-
O
SPVDD
speaker output - pin
SPGND
Open
7
SPOUT+
O
SPVDD
speaker output + pin
SPGND
Open
1
HPL
O
SPVDD
Headphones output Lch terminal
CPGND
Open
40
HPR
O
SPVDD
Headphones output Rch terminal
CPGND
Open
39
CPP
O
CPVDD
Charge pump flying capacitor, positive side output pin
Hi-Z
Open
5
CPN
O
CPVDD
Charge pump flying capacitor, negative side output pin
Hi-Z
Open
19
PLLC
O
HVDD
PLL filter pin
When clock of the MCLKI pin input is used, make it open.
When clock of the SAI_BCLK pin input is used, it is
necessary to connect resistors and a capacitor.
HGND2
Open
31
YP
O
TVDD
YP pin for the touch panel interface
Hi-Z
Open
32
XP
O
TVDD
XP pin for the touch panel interface
Hi-Z
Open
33
XN
O
TVDD
XN pin for the touch panel interface
Hi-Z
Open
34
YN
O
TVDD
YN pin for the touch panel interface
Hi-Z
Open
37
HPCOM
I
-
Headphones amplifier common pin
(input)
-
(Note 1) In case of 2 wire serial, if this pin is used with external pull-up resistor, it possibly gets noise from power.
Therefore, tamper noise design is required
in the noisy environment.
(Note 2) At the time of power down, in HPVDD and HPVSS, is short-circuited.


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