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LTC2327-18 数据表(PDF) 16 Page - Linear Technology

部件名 LTC2327-18
功能描述  True Bipolar, Pseudo-Differential Input ADC with 95dB SNR
Download  26 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2327-18 数据表(HTML) 16 Page - Linear Technology

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LTC2327-18
16
232718fa
For more information www.linear.com/LTC2327-18
applicaTions inForMaTion
Figure 9. Power Supply Current of the LTC2327-18
Versus Sampling Rate
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed. Once the conversion has
completed, the LTC2327-18 powers down.
Acquisition
AproprietarysamplingarchitectureallowstheLTC2327-18
to begin acquiring the input signal for the next conver-
sion 527ns after the start of the current conversion. This
extends the acquisition time to 1.460µs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2327-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 1.5µs.
Auto Nap Mode
The LTC2327-18 automatically enters nap mode after a
conversion has been completed and completely powers
up once a new conversion is initiated on the rising edge of
CNV. During nap mode, only the ADC core powers down
and all other circuits remain active. During nap, data from
the last conversion can be clocked out. The auto nap mode
featurewillreducethepowerdissipationoftheLTC2327-18
as the sampling frequency is reduced. Since full power is
consumed only during a conversion, the ADC core of the
LTC2327-18remainspowereddownforalargerfractionof
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 9.
Sleep Mode
The auto nap mode feature provides limited power savings
since only the ADC core powers down. To obtain greater
power savings, the LTC2327-18 provides a sleep mode.
During sleep mode, the entire part is powered down
except for a small standby current resulting in a power
dissipation of 300μW. To enter sleep mode, toggle CNV
twice with no intervening rising edge on SCK. The part
will enter sleep mode on the falling edge of BUSY from
the last conversion initiated. Once in sleep mode, a rising
edge on SCK will wake the part up. Upon emerging from
sleep mode, wait tWAKE ms before initiating a conversion
to allow the reference and reference buffer to wake up
and charge the bypass capacitors at REFIN and REFBUF.
(Refer to the Timing Diagrams section for more detailed
timing information about sleep mode.)
DIGITAL INTERFACE
The LTC2327-18 has a serial digital interface. The flexible
OVDDsupplyallowstheLTC2327-18tocommunicatewith
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
anexternalclockisappliedtotheSCKpinifSDOisenabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
40MHz, a 500ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2327-18 is simple and
straightforwardtouse.Thefollowingsectionsdescribethe
operation of the LTC2327-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
SAMPLING FREQUENCY (kHz)
0
0
2
4
6
8
10
12
100
200
300
400
232718 F09
500
OVDD
VDD (IN+ = –10.24V)
VDD (IN+ = 10.24V)
VDD (IN+ = 0V)


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