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LTC2327-18 数据表(PDF) 9 Page - Linear Technology

部件名 LTC2327-18
功能描述  True Bipolar, Pseudo-Differential Input ADC with 95dB SNR
Download  26 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2327-18 数据表(HTML) 9 Page - Linear Technology

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LTC2327-18
9
232718fa
For more information www.linear.com/LTC2327-18
pin FuncTions
VDDLBYP (Pin 1): 2.5V Supply Bypass Pin. The voltage
on this pin is generated via an onboard regulator off of
VDD. This pin must be bypassed with a 2.2μF ceramic
capacitor to GND.
VDD(Pin2):5VPowerSupply.TherangeofVDDis4.75Vto
5.25V. Bypass VDD to GND with a 10µF ceramic capacitor.
GND (Pins 3, 6 and 16): Ground.
IN+ (Pin 4): Analog Input. IN+ operates differential with
respect to INwith an IN+-INrange of –2.5 • VREFBUF to
2.5 • VREFBUF.
IN(Pin 5): Analog Ground Sense. INhas an input range
of ±500mV with respect to GND and must be tied to the
ground plane or a remote sense.
REFBUF (Pin 7): Reference Buffer Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 47μF ceramic capacitor. The internal buffer
driving this pin may be disabled by grounding its input
at REFIN. Once the buffer is disabled, an external refer-
ence may overdrive this pin in the range of 2.5V to 5V. A
resistive load greater than 500kΩ can be placed on the
reference buffer output.
REFIN (Pin 8): Reference Output/Reference Buffer Input.
An onboard bandgap reference nominally outputs 2.048V
at this pin. Bypass this pin with a 100nF ceramic capacitor
to GND to limit the reference output noise. If more accu-
racy is desired, this pin may be overdriven by an external
reference in the range of 1.25V to 2.4V.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
CHAIN (Pin 10): Chain Mode Selector Pin. When low,
the LTC2327-18 operates in normal mode and the
RDL/SDI input pin functions to enable or disable SDO.
Whenhigh,theLTC2327-18operatesinchainmodeandthe
RDL/SDI pin functions as SDI, the daisy-chain serial data
input. Logic levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK(Pin13):SerialDataClockInput.WhenSDOisenabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.


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