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LTC2327-16 数据表(PDF) 5 Page - Linear Technology |
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LTC2327-16 数据表(HTML) 5 Page - Linear Technology |
5 / 24 page LTC2327-16 5 232716f For more information www.linear.com/LTC2327-16 aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above VDD or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without latch-up. Note 4: VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V, fSMPL = 500kHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale ±10.24V input with REFIN = 2.048V. Note 9: When REFBUF is overdriven, the internal reference buffer must be turned off by setting REFIN = 0V. Note 10: fSMPL = 500kHz, IREFBUF varies proportionally with sample rate. Note 11: Guaranteed by design, not subject to test. Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 13: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising edge capture. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSMPL Maximum Sampling Frequency l 500 ksps tCONV Conversion Time l 1 1.5 µs tACQ Acquisition Time tACQ = tCYC – tHOLD (Note 11) l 1.460 µs tHOLD Maximum Time between Acquisitions l 540 ns tCYC Time Between Conversions l 2 µs tCNVH CNV High Time l 20 ns tBUSYLH CNV ↑ to BUSY Delay CL = 20pF l 13 ns tCNVL Minimum Low Time for CNV (Note 12) l 20 ns tQUIET SCK Quiet Time from CNV ↑ (Note 11) l 20 ns tSCK SCK Period (Notes 12, 13) l 10 ns tSCKH SCK High Time l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK ↑ (Note 12) l 4 ns tHSDISCK SDI Hold Time From SCK ↑ (Note 12) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 12) l 13.5 ns tDSDO SDO Data Valid Delay from SCK ↑ CL = 20pF, OVDD = 5.25V CL = 20pF, OVDD = 2.5V CL = 20pF, OVDD = 1.71V l l l 7.5 8 9.5 ns ns ns tHSDO SDO Data Remains Valid Delay from SCK ↑ CL = 20pF (Note 11) l 1 ns tDSDOBUSYL SDO Data Valid Delay from BUSY ↓ CL = 20pF (Note 11) l 5 ns tEN Bus Enable Time After RDL ↓ (Note 12) l 16 ns tDIS Bus Relinquish Time After RDL ↑ (Note 12) l 13 ns tWAKE REFBUF Wake-Up Time CREFBUF = 47μF, CREFIN = 100nF 200 ms Figure 1. Voltage Levels for Timing Specifications 0.8 • OVDD 0.2 • OVDD 50% 50% 232716 F01 0.2 • OVDD 0.8 • OVDD 0.2 • OVDD 0.8 • OVDD tDELAY tWIDTH tDELAY |
类似零件编号 - LTC2327-16_15 |
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类似说明 - LTC2327-16_15 |
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