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LF3330QC15 数据表(PDF) 7 Page - LOGIC Devices Incorporated |
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LF3330QC15 数据表(HTML) 7 Page - LOGIC Devices Incorporated |
7 / 15 page DEVICES INCORPORATED Video Imaging Products 7 LF3330 Vertical Digital Image Filter 11/08/2001–LDS.3330-M ADDR1 DATA1 ADDR2 CONFIGURATION REGISTER CLK LD CF11-0 W2 W1: Configuration Register loaded with new data on this rising clock edge. PAUSE DATA1 SELECT REGISTER W1 W2: Select Register loaded with new data on this rising clock edge. Limiting An output limiting function is provided for the output of the filter. The limit registers deter- mine the valid range of output values when limiting is enabled (Bit 0 in Configuration Register 2). There are sixteen 32-bit limit registers. RSL3-0 determines which limit register is used during the limit operation. A value of 0 on RSL3-0 selects limit register 0. A value of 1 selects limit register 1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. RSL3-0 may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is discussed in the LF InterfaceTM section. Coefficient Banks The coefficient banks store the coefficients which feed into the multipliers in the filter. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using the LF InterfaceTM. Coefficient bank loading is discussed in the LF InterfaceTM section. Configuration and Control Registers The configuration registers deter- mine how the LF3330 operates. Tables 2 through 5 show the formats of the four configuration registers. There are three types of control registers: round, select, and limit. There are sixteen round registers. Each round register is 32 bits wide. RSL3-0 determines which round register is used for rounding. There are sixteen select registers. Each select register is 5 bits wide. RSL3-0 determines which select register is used for the select cir- cuitry. There are sixteen limit registers. Each limit register is 32 bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 15-0 and the upper FIGURE 9. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION FIGURE 8. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION ADDR1 COEF0 COEF1 COEFFICIENT SET 1 CLK CF11-0 PAUSE COEF7 LD W1: Configuration Register loaded with new data on this rising clock edge. W1 |
类似零件编号 - LF3330QC15 |
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类似说明 - LF3330QC15 |
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