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LF3310QC12 数据表(PDF) 3 Page - LOGIC Devices Incorporated |
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LF3310QC12 数据表(HTML) 3 Page - LOGIC Devices Incorporated |
3 / 21 page DEVICES INCORPORATED Video Imaging Products 3 LF3310 Horizontal / Vertical Digital Image Filter 11/08/2001-LDS.3310-H SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clock CLK — Master Clock The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 — Data Input DIN11-0 is the 12-bit registered data input port. Data is latched on the rising edge of CLK. HCF11-0 — Horizontal Coefficient Input HCF11-0 is used to load data into the horizontal coefficient banks and the Configuration/Control Registers. Data present on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of CLK when HLD is LOW (see the LF InterfaceTM section for a full discussion). HCA7-0 — Horizontal Coefficient Address HCA7-0 determines which row of data in the horizontal coefficient banks is fed to the multipliers in the horizontal filter. HCA7-0 is latched into the Horizontal Coefficient Address Register on the rising edge of CLK when HCEN is LOW. VCF11-0 — Vertical Coefficient Input VCF11-0 is used to load data into the vertical coefficient banks and the Configuration/Control Registers. Data present on VCF11-0 is latched into the Vertical LF InterfaceTM on the rising edge of CLK when VLD is LOW (see the LF InterfaceTM section for a full discussion). VCA7-0 — Vertical Coefficient Address VCA7-0 determines which row of data in the vertical coefficient banks is fed to the multipliers in the vertical filter. VCA7-0 is latched into the Vertical Coefficient Address Register on the rising edge of CLK when VCEN is LOW. Outputs DOUT11-0 — Data Output DOUT11-0 is the 12-bit registered data output port. Controls HLD — Horizontal Coefficient Load When HLD is LOW, data on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of CLK. When HLD is HIGH, data can not be latched into the Horizontal LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of HLD is required in order for the input circuitry to func- tion properly. Therefore, HLD must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). FIGURE 2. INPUT FORMATS 11 10 9 2 1 0 –2 11 (Sign) 2 10 2 9 2 2 2 1 2 0 11 10 9 2 1 0 –2 0 (Sign) 2 –1 2–2 2 –9 2–10 2–11 Input Data Coefficient Data FIGURE 3. HORIZONTAL AND VERTICAL ACCUMULATOR FORMATS 31 30 29 2 1 0 –2 20 (Sign) 2 19 218 2 –9 2–10 2–11 31 30 29 2 1 0 –2 20 (Sign) 2 19 218 2 –9 2–10 2–11 Horizontal Accumulator Output Vertical Accumulator Output TABLE 1. OUTPUT FORMATS SLCT4-0 S11 S10 S9 · · · S6 S5 · · · S2 S1 S0 00000 F11 F10 F9 · · · F6 F5 · · · F2 F1 F0 00001 F12 F11 F10 · · · F7 F6 · · · F3 F2 F1 00010 F13 F12 F11 · · · F8 F7 · · · F4 F3 F2 · · · · ·· ·· · · · · · ·· ·· · · · · · ·· ·· · 10010 F29 F28 F27 · · · F24 F23 · · · F20 F19 F18 10011 F30 F29 F28 · · · F25 F24 · · · F21 F20 F19 10100 F31 F30 F29 · · · F26 F25 · · · F22 F21 F20 |
类似零件编号 - LF3310QC12 |
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类似说明 - LF3310QC12 |
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