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LTC2408 数据表(PDF) 15 Page - Linear Technology |
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LTC2408 数据表(HTML) 15 Page - Linear Technology |
15 / 36 page 15 LTC2404/LTC2408 APPLICATIONS INFORMATION Table 4. LTC2404/LTC2408 State Duration State Operating Mode Duration CONVERT Internal Oscillator FO = LOW (60Hz Rejection) 133ms FO = HIGH (50Hz Rejection) 160ms External Oscillator FO = External Oscillator 20480/fEOSC (In Seconds) with Frequency fEOSC kHz (fEOSC/2560 Rejection) SLEEP As Long As CS = HIGH Until CS = 0 and SCK DATA OUTPUT Internal Serial Clock FO = LOW/HIGH As Long As CS = LOW But Not Longer Than 1.67ms (Internal Oscillator) (32 SCK cycles) FO = External Oscillator with As Long As CS = LOW But Not Longer Than 256/fEOSCms Frequency fEOSC kHz (32 SCK cycles) External Serial Clock with As Long As CS = LOW But Not Longer Than 32/fSCKms Frequency fSCK kHz (32 SCK cycles) MAXIMUM OUTPUT WORD RATE Figure 4. LTC2404/LTC2408 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) –12 –8 –4 048 12 24048 F04 –60 –70 –80 –90 –100 –110 –120 –130 –140 The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2404/ LTC2408 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2404/LTC2408 provide better than 110dB normal mode rejection in a frequency range fEOSC/2560 ±4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 4. Whenever an external clock is not present at the FO pin the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2404/LTC2408 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 4 summarizes the duration of each state as a function of FO. OWR tt in Hz CONVERT DATAOUTPUT = + 1 |
类似零件编号 - LTC2408 |
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类似说明 - LTC2408 |
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