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MACHLV210-12 数据表(PDF) 27 Page - Lattice Semiconductor |
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MACHLV210-12 数据表(HTML) 27 Page - Lattice Semiconductor |
27 / 29 page 27 MACHLV210-12/15/20 POWER-UP RESET The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing dia- gram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics tPR tWL tS 4 V VCC Power Registered Output Clock 17908D-25 Power-Up Reset Waveform |
类似零件编号 - MACHLV210-12 |
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类似说明 - MACHLV210-12 |
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