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ISPMACH4ACPLDFAMILY 数据表(PDF) 5 Page - Lattice Semiconductor

部件名 ISPMACH4ACPLDFAMILY
功能描述  High Performance E 2 CMOS In-System Programmable Logic
Download  62 Pages
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制造商  LATTICE [Lattice Semiconductor]
网页  http://www.latticesemi.com
标志 LATTICE - Lattice Semiconductor

ISPMACH4ACPLDFAMILY 数据表(HTML) 5 Page - Lattice Semiconductor

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ispMACH 4A Family
5
FUNCTIONAL DESCRIPTION
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized
PAL® blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms
through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the
output switch matrix. In addition, more input routing options are provided by the input switch
matrix. These resources provide the flexibility needed to fit designs efficiently.
Notes:
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do
not connect to the central switch matrix.
I/O
Pins
Clock/Input
Pins
I/O
Pins
I/O
Pins
Dedicated
Input Pins
PAL Block
PAL Block
Logic
Allocator
with XOR
Output/
Buried
Macrocells
33/
34/
36
16
16
Clock
Generator
Logic
Array
Input
Switch
Matrix
16
16
8
Note 1
Note 2
Note 3
4
PAL Block
17466G-001
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure


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