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240VA 数据表(PDF) 5 Page - Lattice Semiconductor |
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240VA 数据表(HTML) 5 Page - Lattice Semiconductor |
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5 / 25 page  5 Specifications ispGDX240VA B30 B31 B32 B33 D26 D27 D28 D29 D30 D31 D32 D33 B26 B27 B28 B29 B32 B33 B34 B35 D28 D29 D30 D31 D28 D29 D30 D31 B24 B25 B26 B27 B31 B32 B33 B34 D27 D28 D29 D30 D29 D30 D31 D32 B25 B26 B27 B28 B29 B30 B31 B32 D25 D26 D27 D28 D31 D32 D33 D34 B27 B28 B29 B30 B28 B29 B30 B31 D24 D25 D26 D27 D32 D33 D34 D35 B28 B29 B30 B31 Data D/ MUXOUT Data C/ MUXOUT Data B/ MUXOUT Data A/ MUXOUT Reflected I/O Cells Normal I/O Cells Table 2. Adjacent I/O Cells (Mapping of ispGDX240VA) It can be seen from Figure 3 that if the D11 adjacent I/O cell is used, the I/O group “A” input is no longer available as a direct MUX input. The ispGDXVA can implement MUXes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent I/O cell outputs with direct MUX inputs. Any particular combination of adjacent I/O cells as MUX inputs will dictate what I/O groups (A, B, C or D) can be routed to the remaining inputs. By properly choosing the adjacent I/O cells, all of the MUX inputs can be utilized. S0 S1 4 x 4 Crossbar Switch .m0 .m1 .m2 .m3 D33 I/O Group A D31 MUX Out I/O Group B D32 MUX Out I/O Group C D34 MUX Out I/O Group D D35 MUX Out ispGDX240VA I/O Cell Figure 3. Adjacent I/O Cells vs. Direct Input Path for ispGDX240VA, I/O D33 Special Features Slew Rate Control All output buffers contain a programmable slew rate control that provides software-selectable slew rate op- tions. Open Drain Control All output buffers provide a programmable Open-Drain option which allows the user to drive system level reset, interrupt and enable/disable lines directly without the need for an off-chip Open-Drain or Open-Collector buffer. Wire-OR logic functions can be performed at the printed circuit board level. Pull-up Resistor All pins have a programmable active pull-up. A typical resistor value for the pull-up ranges from 50k Ω to 80kΩ. Output Latch (Bus Hold) All pins have a programmable circuit that weakly holds the previously driven state when all drivers connected to the pin (including the pin's output driver as well as any other devices connected to the pin by external bus) are tristated. User-Programmable I/Os The ispGDX240VA features user-programmable I/Os supporting either 3.3V or 2.5V output voltage level options. The ispGDX240VA uses a VCCIO pin to provide the 2.5V reference voltage when used. PCI Compatible Drive Capability The ispGDX240VA supports PCI compatible drive capa- bility for all I/Os. |
类似零件编号 - 240VA |
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类似说明 - 240VA |
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