Specifications ispLSI 2128E

5

UNITS

-180

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

Table 2-0030A/2128E

1

1

tsu2 + tco1

(

)

-135

MIN.

MAX.

MAX.

DESCRIPTION

#

2

4

PARAMETER

A

1

Data Prop Delay, 4PT Bypass, ORP Bypass

–

5.0

–

7.5

ns

A

2

Data Prop Delay

––

ns

A

3

180

–

135

–

MHz

–

4

Clk Freq with External Feedback

––

MHz

–

5

Clk Frequency, Max. Toggle

––

MHz

–

6

GLB Reg Setup Time before Clk, 4 PT Bypass

––

ns

A

7

GLB Reg Clk to Output Delay, ORP Bypass

––

ns

–

8

GLB Reg Hold Time after Clk, 4 PT Bypass

0.0

–

ns

–

9

GLB Reg Setup Time before Clk

5.0

–

ns

–

10 GLB Reg Clk to Output Delay

––

ns

–

11 GLB Reg Hold Time after Clk

0.0

–

ns

A

12 External Reset Pin to Output Delay

––

ns

–

13 External Reset Pulse Duration

4.0

–

ns

B

14 Input to Output Enable

––

ns

C

15 Input to Output Disable

––

ns

B

16 Global OE Output Enable

––

ns

C

17 Global OE Output Disable

––

ns

–

18 External Synch Clk Pulse Duration, High

2.5

––

ns

–

19 External Synch Clk Pulse Duration, Low

2.5

––

ns

125

200

4.0

3.0

–

–

3.5

–

7.0

–

10.0

10.0

5.0

5.0

7.5

100

143

5.0

0.0

6.0

0.0

5.0

3.5

3.5

10.0

4.0

4.5

10.0

12.0

12.0

7.0

7.0

-100

MIN. MAX.

–

10.0

–

100

–

–

–

–

–

0.0

8.0

–

0.0

–

6.5

–

–

–

–

5.0

–

5.0

–

77.0

100

6.5

5.0

–

–

6.0

–

13.5

–

15.0

15.0

9.0

9.0

13.0

External Timing Parameters

Over Recommended Operating Conditions