ispLSI

®

2096E

In-System Programmable

SuperFAST™ High Density PLD

2096e_03

1

Features

• SUPERFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 4000 PLD Gates

— 96 I/O Pins, Six Dedicated Inputs

— 96 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional/JEDEC Upward Compatible with

ispLSI 2096 Devices

—

—

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems

— PCI Compatible Outputs

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

November 1998

Description

The ispLSI 2096E is a High Density Programmable Logic

Device. The device contains 96 Registers, 96 Universal

I/O pins, six Dedicated Input pins, three Dedicated Clock

Input pins, two dedicated Global OE input pins and a

Global Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 2096E features 5V in-system programmability

and in-system diagnostic capabilities. The ispLSI 2096E

offers non-volatile reprogrammability of all logic, as well

as the interconnect to provide truly reconfigurable sys-

tems.

The basic unit of logic on the ispLSI 2096E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. C7 (see Figure 1). There are a total of 24 GLBs in the

ispLSI 2096E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or

registered.Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any GLB on the device.

The device also has 96 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, output or bi-

directional I/O pin with 3-state control. The signal levels

are TTL compatible voltages and the output drivers can

source 4 mA or sink 8 mA. Each output can be pro-

grammed independently for fast or slow output slew rate

to minimize overall output switching noise. By connecting

Global Routing Pool

(GRP)

Output Routing Pool (ORP)

Output Routing Pool (ORP)

0919/2096E

C7

C4

C5

C6

A4

A7

A6

A5

GLB

Logic

Array

DQ

DQ

DQ

DQ

Output Routing Pool (ORP)

Output Routing Pool (ORP)

C3

C0

C1

C2

B0

B3

B2

B1

B7

B6

B4

B5

A0

A1

A3

A2