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LTC3240-3.3 数据表(PDF) 10 Page - Linear Technology

部件名 LTC3240-3.3
功能描述  3.3V/2.5V Step-Up/ Step-Down Charge Pump DC/DC Converter
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC3240-3.3 数据表(HTML) 10 Page - Linear Technology

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LTC3240-3.3/LTC3240-2.5
10
3240fb
to additional switch resistance. However, for very light
load applications, the above expression can be used as a
guideline in determining a starting capacitor value.
Ceramic Capacitors
Ceramic capacitors of different materials lose their ca-
pacitance with higher temperature and voltage at differ-
ent rates. For example, a capacitor made of X5R or X7R
material will retain most of its capacitance from – 40°C
to 85°C whereas a Z5U or Y5V style capacitor will lose
considerable capacitance over that range. Z5U and Y5V
capacitors may also have a poor voltage coefficient causing
them to lose 60% or more of their capacitance when the
rated voltage is applied. Therefore when comparing dif-
ferent capacitors, it is often more appropriate to compare
the amount of achievable capacitance for a given case size
rather than discussing the specified capacitance value. For
example, a 4.7µF 10V Y5V ceramic capacitor in a 0805
case only retains 25% of its rated capacitance over tem-
perature with a 3.3V bias, while a 4.7µF 10V X5R ceramic
capacitor will retain 80% of its rated capacitance over the
same conditions. The capacitor manufacturer’s data sheet
should be consulted to ensure the desired capacitance at
all temperatures and voltages.
Below is a list of ceramic capacitor manufacturers and
how to contact them:
AVX
www.avxcorp.com
Kemet
www.kemet.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay
www.vishay.com
TDK
www.component.tdk.com
Layout Considerations
Due to the high switching frequency and high transient
currents produced by LTC3240, careful board layout is
necessary for optimum performance. A true ground plane
and short connections to all the external capacitors will
improve performance and ensure proper regulation under
all conditions. Figure 4 shows an example layout for the
LTC3240.
Figure 4. Recommended Layout
APPLICATIO S I FOR ATIO
COUT
4.7
µF
0603
CIN
1
µF
0603
CFLY
1
µF
0603
GND
VOUT
VIN
3240 F04
SHDN
C
+
C
Thermal Management
For higher input voltages and maximum output current,
there can be substantial power dissipation in the LTC3240.
If the junction temperature increases above approximately
160°C, the thermal shutdown circuitry will automatically
deactivate the output. To reduce the maximum junction
temperature, a good thermal connection to the PC board is
recommended. Connecting GND (Pin 1) and the Exposed
Pad of the DFN package to a ground plane under the device
on two layers of the PC board can reduce the thermal
resistance of the package and PC board considerably.
Derating Power at High Temperatures
To prevent an overtemperature condition in high power
applications, Figure 5 should be used to determine the
maximum combination of ambient temperature and power
dissipation.
The power dissipated in the LTC3240 should always fall
under the line shown for a given ambient temperature.
The power dissipation of the LTC3240 in step-up mode
is given by the expression:
PD = (2VIN – VOUT) • IOUT
The power dissipation in step-down mode is given by:
PD = (VIN – VOUT) • IOUT


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