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LTC1650 数据表(PDF) 7 Page - Linear Technology |
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LTC1650 数据表(HTML) 7 Page - Linear Technology |
7 / 12 page 7 LTC1650 CS/LD (Pin 8): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the CLK signal is enabled so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. CLR (Pin 9): The DAC is cleared to VRST when this pin is pulled low. It should be logic high for normal operation. RSTOUT (Pin 10): The logic output pin that goes active when any of the supplies drop below 2.5V. This pin is active low. REFHI (Pin 11): The Reference Input Pin. The DAC is capable of 4-quadrant multiplying; this pin can swing from 4.5V to – 4V. REFLO F/REFLO S (Pins 12, 13): The Force and Sense Pin for the Lower Reference Input. This should nominally be tied to ground. This pin can swing from – 1V to 1V. AVSS (Pin 14): The Analog Negative Supply Input.– 5.25V ≤AVSS≤–4.75V.Requiresabypasscapacitortoground. AVDD (Pin 15): The Analog Positive Supply Input. 4.75V ≤ AVDD ≤ 5.25V. Requires a bypass capacitor to ground. UNI/BIP (Pin 16): The Unipolar/Bipolar Selection Pin. For unipolar operation, tie this pin to VOUT and for bipolar operation, tie this pin the REFHI. CLK t1 DIN CS/LD DOUT B14 B15 B14 B13 B1 B0 LSB B15 MSB B13 B0 B1 1650 TD (PREVIOUS WORD) t9 t8 t6 t7 t4 t3 t5 t2 PI FU CTIO S TI I G DIAGRA |
类似零件编号 - LTC1650 |
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类似说明 - LTC1650 |
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