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LT1611 数据表(PDF) 8 Page - Linear Technology |
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LT1611 数据表(HTML) 8 Page - Linear Technology |
8 / 12 page 8 LT1611 In Figure 11 (also shown on the first page), output capaci- tor C3 is replaced by a ceramic unit. These large value ceramic capacitors have ESR of about 2m Ω and result in very low output ripple. At the 20mV/division scale, output voltage ripple cannot be seen. Figure 12 pictures the output and switch nodes at 200ns per division. The output voltage ripple is approximately 1mVP–P. Again, good layout is mandatory to achieve this level of performance. OPERATIO Layout The LT1611 switches current at high speed, mandating careful attention to layout for best performance. You will not get advertised performance with careless layout. Figure 13 shows recommended component placement. Follow this closely in your printed circuit layout. The cut ground copper at D1’s cathode is essential to obtain the low noise achieved in Figures 11 and 12’s oscillographs. Input bypass capacitor C1 should be placed close to the LT1611 as shown. The load should connect directly to output capacitor C2 for best load regulation. You can tie the local ground into the system ground plane at C3’s ground terminal. Figure 11. Replacing C3 with 22 µF Ceramic Capacitor (Taiyo Yuden JMK325BJ226MM) Improves Output Noise. CPL = 1200pF Results in Best Phase Margin VOUT 20mV/DIV AC COUPLED LOAD CURRENT 150mA 50mA 100 µs/DIV 1611 F11 Figure 12. 22 µF Ceramic Capacitor at Output Reduces Ripple to 1mVP–P. Proper Layout Is Essential to Achieve Low Noise VOUT 5mV/DIV AC COUPLED SWITCH VOLTAGE 5V/DIV LOAD = 150mA 200ns/DIV 1611 F12 Figure 13. Suggested Component Placement. Note Cut in Ground Copper at D1’s Cathode 1 2 3 5 4 C2 D1 R2 R1 L1B C1 L1A + SHUTDOWN 1611 F13 –VOUT GND VIN C3 |
类似零件编号 - LT1611 |
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类似说明 - LT1611 |
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