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ADV7191 数据表(PDF) 6 Page - Analog Devices |
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ADV7191 数据表(HTML) 6 Page - Analog Devices |
6 / 72 page ADV7190/ADV7191 –6– REV. B 5 V TIMING CHARACTERISTICS Parameter Min Typ Max Unit Test Conditions MPU PORT 2 SCLOCK Frequency 0 400 kHz SCLOCK High Pulsewidth, t1 0.6 ms SCLOCK Low Pulsewidth, t2 1.3 ms Hold Time (Start Condition), t3 0.6 ms After This Period, the First Clock is Generated Setup Time (Start Condition), t4 0.6 msRelevant for Repeated Start Condition Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 ms ANALOG OUTPUTS 2 Analog Output Delay 8 ns DAC Analog Output Skew 0.1 ns CLOCK CONTROL AND PIXEL PORT 3 fCLOCK 27 MHz Clock High Time, t9 8ns Clock Low Time, t10 8ns Data Setup Time, t11 6ns Data Hold Time, t12 5ns Control Setup Time, t11 6ns Control Hold Time, t12 4ns Digital Output Access Time, t13 13 ns Digital Output Hold Time, t14 12 ns Pipeline Delay, t15 (2 ¥ Oversampling) 57 Clock Cycles Pipeline Delay, t15 (4 ¥ Oversampling) 67 Clock Cycles TELETEXT PORT 4 Digital Output Access Time, t16 11 ns Data Setup Time, t17 3ns Data Hold Time, t18 6ns RESET CONTROL RESET Low Time 3 20 ns PLL 2 PLL Output Frequency 54 MHz NOTES 1Temperature range T MIN to TMAX: 0 ∞C to 70∞C. 2Guaranteed by characterization. 3Pixel Port consists of: Data: P15–P0 Pixel Inputs, Control: HSYNC, VSYNC, BLANK, Clock: CLKIN Input. 4Teletext Port consists of: Digital Output: TTXREQ, Data: TTX. Specifications subject to change without notice. (VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 , unless otherwise noted. All specifications TMIN to TMAX 1, unless otherwise noted.) |
类似零件编号 - ADV7191_15 |
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类似说明 - ADV7191_15 |
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