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ADV7162 数据表(PDF) 8 Page - Analog Devices |
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ADV7162 数据表(HTML) 8 Page - Analog Devices |
8 / 44 page REV. 0 –8– ADV7160/ADV7162 t10 AN ... DN AN+1 ... DN+1 AN+2 ... DN+2 DIGITAL INPUT TO ANALOG OUTPUT PIPELINE AN+2 ... DN+2 AN+1 ... DN+1 AN ... DN AN–1 ... DN–1 tPD CLOCK LOADOUT LOADIN PIXEL INPUT DATA ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT) Figure 7. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (4:1 Multiplex Mode) AN ... DN AN+1 ... DN+1 AN+2 ... DN+2 DIGITAL INPUT TO ANALOG OUTPUT PIPELINE AN+2 ... DN+2 AN+1 ... DN+1 AN ... DN AN–1 ... DN–1 tPD CLOCK LOADOUT LOADIN PIXEL INPUT DATA τ τ-t 11 ANALOG OUTPUT DATA (IOR, IOG, IOB, SYNCOUT) Figure 8. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (4:1 Multiplex Mode) |
类似零件编号 - ADV7162_15 |
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类似说明 - ADV7162_15 |
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