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ISL5239 数据表(PDF) 11 Page - Intersil Corporation

部件名 ISL5239
功能描述  Pre-Distortion Linearizer
Download  31 Pages
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制造商  INTERSIL [Intersil Corporation]
网页  http://www.intersil.com/cda/home
标志 INTERSIL - Intersil Corporation

ISL5239 数据表(HTML) 11 Page - Intersil Corporation

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For the input data, the 0x04, bit 3 input data round bit must
also be selected and the feedback memory length count is
always set to 1024. To invoke memory operation, the 0x07,
bit 4 feedback memory mode or bits 1:0 input memory mode
and 0x04, bit 6 processor trigger must be controlled.
There are three modes of operation — capture, loop, and
single-shot. The feedback memory does not have a loop
mode. A synopsis of the three modes is described below.
Capture Mode
There are two types of capture mode — advanced trigger
and single/capture. The advanced trigger mode allows data
to be captured around a trigger point, and the quantity of the
data captured after the trigger point is set by 0x06, bits 14:0.
When input memory capture mode = DELAY, the delay
register acts as a delay count prior to the capture or sending
of data. The max delay in this case is 32768 counts or
system clock ticks. The advanced trigger mode is used in
capture mode only. With the feedback capture operations
being analogous to the input memory, one feedback memory
exception is its control register 0x08, bits 14:0. It has 10
LSBs of available capture space.
Advanced Trigger Capture Mode Sequence
The control register 0x0e, bit 13:12 input capture status,
should be in IDLE. Set 0x06, bit 15, input memory capture
mode to ADVANCE to signify an advanced trigger capture.
0x06, bits 14:0 set the input trigger delay counter to = 0x56
signifies there are 86 points captured after the occurrence of
the trigger point, 0x0e, bit 10:0, input trigger position and all
other points are captured prior to trigger point. Note: only the
11 lsbs are valid for the delay capture in this mode. The input
trigger position is a read-only register and adding to it the 11
lsbs of the input trigger delay counter determines the
position of the final data point captured after the trigger. If the
input trigger position is 0x1ff, the final point captured
occurred at address: 0x1ff + 0x56 = 0x255 or 597 (decimal).
The user must set the input trigger delay counter prior to
invoking the transaction of the capture.
The user invokes the capture mode register by writing
CAPTURE to 0x07, bit 1:0 input memory mode. The system
is in the advanced trigger capture mode and 0x0e, bits
13:12, input capture status is ARMED. The system waits for
a trigger as the memory is continuously being written into.
When a trigger occurs, the trigger causes the memory to
load the data till the memory address is equal to input trigger
position + 11 lsbs of the input trigger delay counter. The
memory address that is time coincident with the trigger
occurrence latches to the input trigger position. During this
period, the input capture status is LOADING. When the final
capture point loads, the input capture status returns to IDLE
and a new capture transaction can be initiated by writing
CAPTURE to the input memory mode.
Single/Capture Mode
The sequence for the single shot stimulus mode, input
memory mode = SINGLE, and input memory capture mode
= CAPTURE with input capture mode = DELAY are the
identical. The function of the memory reading or writing
provides the difference between the two modes. In the single
shot case, the capture memories read data to the output bus,
and in the capture mode, they write data to the memories.
The sequence of operation in the Single/Capture mode is
described below.
The input capture status should be in IDLE and the input
memory capture mode in DELAY with the input memory
delay counter set to 0x0056. Note: The 15 LSBs of the input
memory delay counter are valid for the delay count in this
mode. After the trigger, Ox56 signifies there are 86 counts of
delay before the start of the capture/send of data to/from the
memory.
The user invokes the capture mode by writing the input
memory mode to CAPTURE. The system is in the capture
mode and the input memory status is ARMED. The system
waits for a trigger and the memory is idle at this point. When
a trigger occurs, the trigger causes the delay counters to
count 86 clocks of delay. At the end of the delay, the
memories begin their writing sequence until input memory
length data points are written. During the writing of data, the
input memory status is LOADING. When the final input
memory length point is written, the input memory status
returns to IDLE and a new capture transaction can be
initiated by writing CAPTURE to the input memory mode.
For the Single Capture mode, the deviations from the
sequence are the writing of the input memory mode to
SINGLE, and the input memory status to SEND when
reading of the data from memory. All other operations are
analogous.
Loop Mode
This is a continuous play mode from the memories;
therefore, the memories should contain valid data before
invoking transactions. The length of each repeatable output
stream is controlled by the input memory length. Upon
outputting the final input memory length point, the hardware
resets to play another set of input memory length points from
the memory.
The user invokes the loop mode by writing input memory
mode to LOOP. The system is in the loop mode and the input
memory status = SEND. The memory starts reading data
continuously and a stop can be initiated by setting input
memory mode to IDLE during the transaction. The input
memory status returns to IDLE and a new loop transaction
can be initiated by writing the input memory mode to LOOP.
This is the only mode where immediate mode changes are
acknowledged during its transaction cycle.
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