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ADMCF340 数据表(PDF) 8 Page - Analog Devices

部件名 ADMCF340
功能描述  64-Lead Flash and ROM Memory
Download  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADMCF340 数据表(HTML) 8 Page - Analog Devices

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REV. A
ADMC(F)340
–8–
PM ROM
4K
24
PM RAM
512
24
BUS
EXCHANGE
COMPANDING
CIRCUITRY
DATA
ADDRESS
GENERATOR
No. 2
DATA
ADDRESS
GENERATOR
No. 1
14
14
24
16
6
DM RAM
512
16
R BUS
16
DMA BUS
PMA BUS
DMD BUS
PMD BUS
INSTRUCTION
REGISTER
INPUT REGS
OUTPUT REGS
SHIFTER
CONTROL
LOGIC
SERIAL
PORT
RECEIVE REG
TRANSMIT REG
TIMER
INPUT REGS
OUTPUT REGS
MAC
INPUT REGS
OUTPUT REGS
ALU
PROGRAM
SEQUENCER
FLASH
PROGRAM
MEMORY
4K
24
Figure 3. DSP Core Block Diagram
GENERAL DESCRIPTION
The ADMC(F)340 is a low cost, single-chip DSP-based
controller suitable for permanent magnet synchronous, ac
induction, switched reluctance, and brushless dc motors. The
ADMC(F)340 integrates a 20 MHz, fixed-point DSP core with
a complete set of motor control and system peripherals for fast,
efficient development of motor controllers.
The DSP core of the ADMC(F)340 is completely code compatible
with the ADSP-21xx DSP family and combines three computa-
tional units, data address generators, and a program sequencer.
The computational units comprise an ALU, a multiplier/accumu-
lator (MAC), and a barrel shifter. There are special instructions
for bit manipulation, multiplication (x squared), biased rounding,
and global interrupt masking. The system peripherals are the
power-on reset circuit (POR), the watchdog timer, and two
synchronous serial ports. The serial ports are configurable
and double buffered, with hardware support for UART, SCI,
and SPI port emulation. The ADMC(F)340 provides 512
× 24-bit
program memory RAM, 4K
× 24-bit program memory ROM,
4K
× 24-bit program FLASH memory, and 512 × 16-bit data
memory RAM. The user code will be stored and executed from
the flash memory. The program and data memory RAM can be
used for dynamic data storage or can be loaded through the
serial port from an external device as in other ADMCxx family
parts. The program memory ROM contains a monitor function
as well as useful routines for erasing, programming, and verifying
the flash memory.
The motor control peripherals of the ADMC(F)340 provide a 12-bit
analog data acquisition system with 13 analog input channels,
three dedicated ISENSE functions (combining internal amplifi-
cation, sampling, and overcurrent PWM shutdown features),
and an internal voltage reference. In addition, a three-phase,
16-bit, center-based PWM generation unit can be used to produce
high accuracy PWM signals with minimal processor overhead. The
ADMC(F)340 also contains two 16-bit auxiliary PWM timers
and 25 lines of programmable digital I/O.
Several functions, such as the auxiliary PWM and the serial
communication ports, are multiplexed with the nine PORTA
(9, PIO) programmable input/output (PIO) pins. The other 16
programmable digital I/O pins are dedicated. The pin functions
can be independently selected to allow maximum flexibility
for different applications.
(continued from page 1)
External
PWMTRIP Pin
Switched Reluctance Motor Mode Selection Pin
PWM Polarity Selection Pin
Integrated 13-Channel ADC Subsystem
3 Bipolar ISENSE Inputs with Programmable
Sample-and-Hold Amplifier and Overcurrent
Protection (Usable as 3 Dedicated Analog Inputs)
3 Simultaneous Converting Voltage Inputs
7 Muxed Auxiliary Analog Inputs
Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching
Frequency
25-Lead Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
2 16-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
2 Programmable Operation Modes
Independent Mode/Offset Mode


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