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ADF4118 数据表(PDF) 5 Page - Analog Devices |
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ADF4118 数据表(HTML) 5 Page - Analog Devices |
5 / 28 page ADF4116/ADF4117/ADF4118 Rev. D | Page 5 of 28 TIMING CHARACTERISTICS AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Guaranteed by design, but not production tested. Table 2. Parameter Limit at TMIN to TMAX (B, Y Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLK setup time t2 10 ns min DATA to CLK hold time t3 25 ns min CLK high duration t4 25 ns min CLK low duration t5 10 ns min CLK to LE setup time t6 20 ns min LE pulse width CLK DATA LE LE DB20 (MSB) DB19 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t5 t2 t4 t6 t1 t3 Figure 2. Timing Diagram |
类似零件编号 - ADF4118_15 |
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类似说明 - ADF4118_15 |
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