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ADE7759 数据表(PDF) 11 Page - Analog Devices |
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ADE7759 数据表(HTML) 11 Page - Analog Devices |
11 / 36 page REV. A ADE7759 –11– GAIN (CH1) RB 1 4 10 2.5 VDD 10 F10 F 100nF 100nF AVDD DVDD RESET DIN DOUT SCLK CS CLKOUT CLKIN IRQ SAG ZX CF AGND DGND V1P V1N V2N V2P REFIN/OUT U1 ADE7759 TO SPI BUS (USED ONLY FOR CALIBRATION) 22pF 22pF Y1 3.58MHz NOT CONNECTED U3 TO FREQUENCY COUNTER PS2501-1 I 1k 33nF 1k 33nF 1k 33nF 600k 110V 1k 33nF 10 F 100nF RB CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 1 Test Circuit 1. Performance Curve (Integrator OFF) VDD 10 F10 F 100nF 100nF AVDD DVDD RESET DIN DOUT SCLK CS CLKOUT CLKIN IRQ SAG ZX CF AGND DGND V1P V1N V2N V2P REFIN/OUT U1 ADE7759 TO SPI BUS (USED ONLY FOR CALIBRATION) 22pF 22pF Y1 3.58MHz NOT CONNECTED U3 PS2501-1 I di/dt CURRENT SENSOR 100 1k 33nF 33nF 100 1k 33nF 33nF 1k 33nF 600k 110V 1k 33nF 10 F 100nF CHANNEL 1 GAIN = 4 CHANNEL 2 GAIN = 1 TO FREQUENCY COUNTER Test Circuit 2. Performance Curve (Integrator ON) ANALOG INPUTS The ADE7759 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N are ± 0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/V2N are ±0.5 V with respect to AGND. Each analog input channel has a PGA (Programmable Gain Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the gain register—see Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1 and the gain selection for the PGA in Channel 2 is made via Bits 5 to 7. Figure 4 shows how a gain selection for Channel 1 is made using the gain register. V1P V1N V IN K V IN + GAIN[7:0] GAIN (K) SELECTION OFFSET ADJUST ( 50mV) CH1OS[7:0] BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION BIT 6: NOT USED BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON) Figure 4. PGA in Channel 1 In addition to the PGA, Channel 1 also has a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register—see Figure 5. As mentioned previously the maximum differential input voltage is 0.5 V. However, by using Bits 3 and 4 in the gain register, the maximum ADC input voltage can be set to 0.5 V, 0.25 V, or 0.125 V. This is achieved by adjusting the ADC reference—see Reference Circuit section. Table I summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections. Table I. Maximum Input Signal Levels for Channel 1 Max Signal ADC Input Range Selection Channel 1 0.5 V 0.25 V 0.125 V 0.5 V Gain = 1 0.25 V Gain = 2 Gain = 1 0.125 V Gain = 4 Gain = 2 Gain = 1 0.0625 V Gain = 8 Gain = 4 Gain = 2 0.0313 V Gain = 16 Gain = 8 Gain = 4 0.0156 V Gain = 16 Gain = 8 0.00781 V Gain = 16 GAIN REGISTER* CHANNEL 1 AND CHANNEL 2 PGA CONTROL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ADDR: 0AH *REGISTER CONTENTS SHOW POWER-ON DEFAULTS PGA 2 GAIN SELECT 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 PGA 1 GAIN SELECT 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 CHANNEL 1 FULL-SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V Figure 5. Analog Gain Register Test Circuits |
类似零件编号 - ADE7759_15 |
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类似说明 - ADE7759_15 |
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