AD9920A_15 datasheet(4/112 Pages) AD

部件名	AD9920A

功能描述	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

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制造商	AD [Analog Devices]

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AD9920A

Rev. B | Page 4 of 112

SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating

−25

+85

°C

Storage

−65

+150

°C

POWER SUPPLY VOLTAGE INPUTS

AVDD

AFE analog supply

1.6

1.8

2.0

V

TCVDD

Timing core supply

1.6

1.8

2.0

V

CLIVDD

CLI input supply

1.6

3.0

3.6

V

RGVDD

RG, HL driver supply

2.1

3.0

3.6

V

HVDD1 and HVDD2

H1 to H8 driver supplies

2.1

3.0

3.6

V

DVDD

Digital logic supply

1.6

1.8

2.0

V

DRVDD

Parallel data output driver supply

1.6

3.0

3.6

V

IOVDD

Digital I/O supply

1.6

3.0

3.6

V

V-DRIVER POWER SUPPLY VOLTAGES

VDVDD

V-driver/logic supply

1.6

3.0

3.6

V

VH1, VH2

V-driver high supply

11.0

15.0

16.5

V

VL1, VL2

V-driver low supply

−8.5

−7.5

−5.5

V

VM1, VM2

V-driver midsupply

−1.5

0.0

+1.5

V

VLL

SUBCK low supply

−11.0

−7.5

−5.5

V

VH1, VH2 to VL1, VL2, VLL

23.5

V

VMM1

SUBCK midsupply

VLL

0.0

VDVDD

V

LDO2

LDOIN

LDO supply input

2.5

3.0

3.6

V

Output Voltage

1.8

1.9

2.05

V

Output Current

60

100

mA

POWER SUPPLY CURRENTS—40.5 MHz

OPERATION

AVDD

1.8 V

27

mA

TCVDD

1.8 V

5

mA

CLIVDD

3 V

1.5

mA

RGVDD

3.3 V, 20 pF RG load, 20 pF HL load

10

mA

HVDD1 and HVDD23

3.3 V, 480 pF total load on H1 to H8

59

mA

DVDD

1.8 V

9.5

mA

DRVDD

3 V, 10 pF load on each data output pin

(D0 to D11)

6

mA

IOVDD

3 V, depends on load and output

frequency of digital I/O

2

mA

POWER SUPPLY CURRENTS—STANDBY

MODE OPERATION

Standby1 Mode

20

mA

Standby2 Mode

5

mA

Standby3 Mode

1.5

mA

MAXIMUM CLOCK RATE (CLI)

40.5

MHz

MINIMUM CLOCK RATE (CLI)

10

MHz

1 VMM must be greater than VLL and less than VDVDD.

2 LDO should be used only for the AD9920A 1.8 V supplies, not for external circuitry.

3 The total power dissipated by the HVDD (or RGVDD) can be approximated using the following equation:

Total HVDD Power = (CL × HVDD × Pixel Frequency) × HVDD

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