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AD9540 数据表(PDF) 1 Page - Analog Devices |
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AD9540 数据表(HTML) 1 Page - Analog Devices |
1 / 32 page 655 MHz Low Jitter Clock Generator AD9540 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES Excellent intrinsic jitter performance 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable) Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable) 8 programmable phase/frequency profiles 400 MSPS internal DDS clock speed 48-bit frequency tuning word resolution 14-bit programmable phase offset 1.8 V supply for device operation 3.3 V supply for I/O, CML driver, and charge pump output Software controlled power-down 48-lead LFCSP_VQ package Programmable charge pump current (up to 4 mA) Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant output driver APPLICATIONS Clocking high performance data converters Base station clocking applications Network (SONET/SDH) clocking Gigabit Ethernet (GbE) clocking Instrumentation clocking circuits Agile LO frequency synthesis Automotive radar FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND CP_VDD CP_RSET CP REF, AMP REFIN REFIN CLK1 CLK1 CHARGE PUMP PHASE FREQUENCY DETECTOR M DIVIDER N DIVIDER DIVIDER 1, 2, 4, 8 SYNC_IN/STATUS SYNC, PLL LOCK SCLK SDI/O SDO CS SERIAL CONTROL PORT TIMING AND CONTROL LOGIC CLK2 CP_OUT CLK2 DRV_RSET OUT0 CML OUT0 CLK DIVCLK S2 S1 S0 PHASE/ FREQUENCY PROFILES DDS IOUT IOUT DAC DAC_RSET 48 10 14 AD9540 Figure 1. |
类似零件编号 - AD9540_15 |
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类似说明 - AD9540_15 |
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