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AD9518-4 数据表(PDF) 2 Page - Analog Devices |
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AD9518-4 数据表(HTML) 2 Page - Analog Devices |
2 / 61 page AD9518-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 6 Clock Outputs............................................................................... 6 Timing Characteristics ................................................................ 6 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 7 Clock Output Absolute Phase Noise (Internal VCO Used).... 7 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)............................................................................... 8 Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)............................................................................... 8 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ........................................................................... 8 Clock Output Additive Time Jitter (VCO Divider Not Used) 9 Clock Output Additive Time Jitter (VCO Divider Used) ....... 9 Serial Control Port ..................................................................... 10 PD, SYNC, and RESET Pins ..................................................... 10 LD, STATUS, and REFMON Pins............................................ 11 Power Dissipation....................................................................... 11 Timing Diagrams............................................................................ 12 Absolute Maximum Ratings.......................................................... 13 Thermal Resistance .................................................................... 13 ESD Caution................................................................................ 13 Pin Configuration and Function Descriptions........................... 14 Typical Performance Characteristics ........................................... 16 Terminology.................................................................................... 20 Detailed Block Diagram ................................................................ 21 Theory of Operation ...................................................................... 22 Operational Configurations...................................................... 22 Digital Lock Detect (DLD) ....................................................... 30 Clock Distribution ..................................................................... 34 Reset Modes ................................................................................ 38 Power-Down Modes .................................................................. 38 Serial Control Port ......................................................................... 40 Serial Control Port Pin Descriptions....................................... 40 General Operation of Serial Control Port............................... 40 The Instruction Word (16 Bits)................................................ 41 MSB/LSB First Transfers ........................................................... 41 Thermal Performance.................................................................... 44 Control Registers............................................................................ 45 Control Register Map Overview .............................................. 45 Control Register Map Descriptions ......................................... 47 Applications Information .............................................................. 59 Frequency Planning Using the AD9518.................................. 59 Using the AD9518 Outputs for ADC Clock Applications.... 59 LVPECL Clock Distribution..................................................... 60 Outline Dimensions....................................................................... 61 Ordering Guide .......................................................................... 61 Rev. D | Page 2 of 61 |
类似零件编号 - AD9518-4_15 |
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类似说明 - AD9518-4_15 |
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