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AD9516-2 数据表(PDF) 7 Page - Analog Devices |
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AD9516-2 数据表(HTML) 7 Page - Analog Devices |
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7 / 80 page  Data Sheet AD9516-2 Rev. C | Page 7 of 80 TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 43 Clock Distribution Configuration 773 933 1090 ps See Figure 45 Variation with Temperature 0.8 ps/°C OUTPUT SKEW, LVPECL OUTPUTS1 LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps LVDS Termination = 100 Ω differential; 3.5 mA Output Rise Time, tRL 170 350 ps 20% to 80%, measured differentially2 Output Fall Time, tFL 160 350 ps 20% to 80%, measured differentially2 PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT Delay off on all outputs OUT6, OUT7, OUT8, OUT9 For All Divide Values 1.4 1.8 2.1 ns Variation with Temperature 1.25 ps/°C OUTPUT SKEW, LVDS OUTPUTS1 Delay off on all outputs LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps CMOS Termination = open Output Rise Time, tRC 495 1000 ps 20% to 80%; CLOAD = 10 pF Output Fall Time, tFC 475 985 ps 80% to 20%; CLOAD = 10 pF PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT Fine delay off For All Divide Values 1.6 2.1 2.6 ns Variation with Temperature 2.6 ps/°C OUTPUT SKEW, CMOS OUTPUTS1 Fine delay off CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps DELAY ADJUST3 LVDS and CMOS Shortest Delay Range4 Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 101111b Zero Scale 50 315 680 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b Full Scale 540 880 1180 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b Longest Delay Range4 Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 000000b Zero Scale 200 570 950 ps Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b Quarter Scale 1.72 2.31 2.89 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b Full Scale 5.7 8.0 10.1 ns Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b Delay Variation with Temperature Short Delay Range5 Zero Scale 0.23 ps/°C Full Scale −0.02 ps/°C Long Delay Range5 Zero Scale 0.3 ps/°C Full Scale 0.24 ps/°C 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Corresponding CMOS drivers set to A for noninverting and B for inverting. 3 The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation. |
类似零件编号 - AD9516-2_15 |
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类似说明 - AD9516-2_15 |
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