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AD9230 数据表(PDF) 9 Page - Analog Devices

部件名 AD9230
功能描述  12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
Download  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9230 数据表(HTML) 9 Page - Analog Devices

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AD9230
Rev. 0 | Page 9 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
D3–
2
D3+
3
D4–
4
D4+
5
D5–
6
D5+
7
DRVDD
8
DRGND
9
D6–
10
D6+
11
D7–
12
D7+
13
D8–
14
D8+
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9230
Figure 4. Single Data Rate Mode
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic
Description
30, 32 to 34, 37 to 39,
41 to 43, 46
AVDD
1.8 V Analog Supply.
7, 24, 47
DRVDD
1.8 V Digital Output Supply.
0
AGND1
Analog Ground.
8, 23, 48
DRGND1
Digital Output Ground.
35
VIN+
Analog Input—True.
36
VIN−
Analog Input—Complement.
40
CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44
CLK+
Clock Input—True.
45
CLK−
Clock Input—Complement.
31
RBIAS
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
28
RESET
CMOS-Compatible Chip Reset (Active Low).
25
SDIO/DCS
Serial Port Interface (SPI®) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
26
SCLK/DFS
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27
CSB
Serial Port Chip Select (Active Low).
29
PWDN
Chip Power-Down.
49
DCO−
Data Clock Output—Complement.
50
DCO+
Data Clock Output—True.
51
D0−
D0 Complement Output Bit (LSB).
52
D0+
D0 True Output Bit (LSB).
53
D1−
D1 Complement Output Bit.
54
D1+
D1 True Output Bit.
55
D2−
D2 Complement Output Bit.
56
D2+
D2 True Output Bit.
1
D3−
D3 Complement Output Bit.
2
D3+
D3 True Output Bit.
3
D4−
D4 Complement Output Bit.
4
D4+
D4 True Output Bit.


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