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AD8300 数据表(PDF) 1 Page - Analog Devices |
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AD8300 数据表(HTML) 1 Page - Analog Devices |
1 / 8 page REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD8300 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 FUNCTIONAL BLOCK DIAGRAM VDD VOUT GND CLR LD CS CLK SDI AD8300 12 12 12-BIT DAC REF DAC REGISTER EN SERIAL REGISTER +3 Volt, Serial Input Complete 12-Bit DAC FEATURES Complete 12-Bit DAC No External Components Single +3 Volt Operation 0.5 mV/Bit with 2.0475 V Full Scale 6 s Output Voltage Settling Time Low Power: 3.6 mW Compact SO-8 1.5 mm Height Package APPLICATIONS Portable Communications Digitally Controlled Calibration Servo Controls PC Peripherals GENERAL DESCRIPTION The AD8300 is a complete 12-bit, voltage-output digital-to- analog converter designed to operate from a single +3 volt sup- ply. Built using a CBCMOS process, this monolithic DAC offers the user low cost, and ease-of-use in single-supply +3 volt systems. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V making this device ideal for battery oper- ated applications. The 2.0475 V full-scale voltage output is laser trimmed to maintain accuracy over the operating temperature range of the device. The binary input data format provides an easy-to-use one-half-millivolt-per-bit software programmability. The voltage outputs are capable of sourcing 5 mA. A double buffered serial data interface offers high speed, three- wire, DSP and microcontroller compatible inputs using data in (SDI), clock (CLK) and load strobe ( LD) pins. A chip select ( CS) pin simplifies connection of multiple DAC packages by enabling the clock input when active low. Additionally, a CLR input sets the output to zero scale at power on or upon user demand. The AD8300 is specified over the extended industrial (–40 °C to +85 °C) temperature range. AD8300s are available in plastic DIP, and low profile 1.5 mm height SO-8 surface mount packages. 3.0 2.8 2.0 0.01 10 0.1 1.0 2.6 2.4 2.2 OUTPUT LOAD CURRENT – mA PROPER OPERATION WHEN VDD SUPPLY VOLTAGE ABOVE CURVE VFS 1 LSB DATA = FFFH TA = +25 C Figure 1. Minimum Supply Voltage vs. Load 1.00 0.75 –1.00 0 4096 1024 2048 0.50 3072 0.25 0.00 –0.25 –0.50 –0.75 DIGITAL INPUT CODE – Decimal VDD = +2.7V TA = –40 C, +25 C, +125 C = –40 C = +25 C = +125 C Figure 2. Linearity Error vs. Digital Code and Temperature |
类似零件编号 - AD8300_15 |
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类似说明 - AD8300_15 |
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