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AD8184 数据表(PDF) 7 Page - Analog Devices |
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AD8184 数据表(HTML) 7 Page - Analog Devices |
7 / 12 page AD8184 –7– REV. 0 series resistors at the input or output. If better flatness response is desired, an input series resistance (RS) may be used (refer to Figure 19), although this will increase crosstalk. The dc gain of the AD8184 is almost independent of load for RL > 10 k Ω. For heavier loads, the dc gain is approximately that of the voltage divider formed by the output impedance of the mux (typically 28 Ω and R L). High speed disable clamp circuits (not shown) at the bases of Q3 and Q4 allow the buffers to turn off quickly and cleanly without dissipating much power once off. Moreover, these clamps shunt displacement currents flowing through the junc- tion capacitances of Q1 and Q2 away from the bases of Q3 and Q4 and to ac ground through low impedances. The two-pole high-pass frequency response of the T switch formed by these clamps is a significant improvement over the one-pole high pass response of a simple series CMOS switch. As a result, board and package parasitics, especially stray capacitance between inputs and outputs, may limit the achievable crosstalk and off isolation. LAYOUT CONSIDERATIONS: Realizing the high speed performance attainable with the AD8184 requires careful attention to board layout and compo- nent selection. Proper RF design techniques and low parasitic component selection are mandatory. Wire wrap boards, prototype boards and sockets are not recom- mended because of their high parasitic inductance and capaci- tance. Instead, surface-mount components should be directly soldered to a printed circuit board (PCB). The PCB should have a ground plane covering all unused portions of the compo- nent side of the board to provide a low impedance ground path. To reduce stray capacitance the ground plane should be removed from the area near input and output pins. THEORY OF OPERATION The AD8184 video multiplexer is designed for fast switching (10 ns) and wide bandwidth (> 700 MHz). This performance is attained with low power dissipation (4.4 mA, enabled) through the use of proprietary circuit techniques and a dielectrically- isolated complementary bipolar process. This device has a fast disable function that allows the outputs of several muxes to be wired in parallel to form a larger mux with little degradation in switching time. The low disabled output capacitance (3.2 pF) helps to preserve the system bandwidth in larger matrices. Un- like earlier CMOS switches, the switched open-loop buffer ar- chitecture of the AD8184 provides a unidirectional signal path with minimal switching glitches and constant, low input capaci- tance. Since the input impedance of these muxes is nearly inde- pendent of the load impedance and the state of the mux, the frequency response of the ON channels in a large switch matrix is not affected by fanout. Figure 21 shows a block diagram and simplified schematic of the AD8184, which contains four switched buffers (S0–S3) that share a common output. The decoder logic translates TTL- compatible logic inputs (A0, A1 and ENABLE) to internal, dif- ferential ECL levels for fast, low-glitch switching. The A0 (LSB) and A1 (MSB) control inputs constitute a two-bit binary word that determines which of the four buffers is enabled, unless the ENABLE input is HIGH, in which case all buffers are disabled and the output is switched to a high impedance state. Each open-loop buffer is implemented as a complementary emitter follower that provides high input impedance, symmetric slew rate and load drive, and high output-to-input isolation due to its β2 current gain. The selected buffer is biased ON by fast switched current sources that allow the buffer to turn on quickly. Dedicated flatness circuits, combined with the open-loop archi- tecture of the AD8184, keep peaking low (typically < 0.5 dB) when driving high capacitive loads, without the need for external AD8184 1 IN0 S3 I1 I2 Q2 Q1 Q3 Q4 6 S2 I1 I2 Q2 Q1 Q3 Q4 S1 I1 I2 Q2 Q1 Q3 Q4 S0 I1 I2 Q2 Q1 Q3 Q4 2 GND 3 IN1 5 IN2 GND 4 GND 7 IN3 14 13 12 11 10 9 8 VEE NC OUT A1 A0 VCC NC = NO CONNECT Figure 21. Block Diagram and Simplified Schematic of the AD8184 Multiplexer |
类似零件编号 - AD8184_15 |
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类似说明 - AD8184_15 |
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