7-883

CD4043BMS, CD4044BMS

FIGURE 8. SWITCH BOUNCE ELIMINATOR

FIGURE 9. ENABLE PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORM

FIGURE 7. TYPICAL POWER DISSIPATION vs FREQUENCY

TEST

IN

IN

A

tPHZ

VDD

VSS

VSS

tPLZ

VSS

VDD

VDD

tPZH

VDD

VSS

VSS

tPZL

VSS

VDD

VDD

Z = HIGH IMPEDANCE

10V

5V

10V

SUPPLY VOLTAGE (VDD) = 15V

10

1

INPUT FREQUENCY (fI) (kHz)

CL = 50pF

CL =15pF

LATCH

SQ

R

LATCH

SQ

R

OUTPUT

OUTPUT

1M

Ω

1M

Ω

1M

Ω

1M

Ω

VDD

VDD

VDD

CD4044BMS

CD4043BMS

14

15

16

13

12

11

10

9

1

2

3

4

5

7

6

8

ENABLE

A

VDD

IN

IN

1K

Ω

CL = 50pF

VSS

50%

50%

VDD

ENABLE

tPZH

tPHZ

tPLZ

tPZL

90%

10%

90%

10%

POINT A

(IN = VDD, IN = VSS)

POINT A

(IN = VSS, IN = VDD)

VSS

≈ 2/3 VDD

≈ 1/3 VDD

≈ 2/3 VDD

≈ 1/3 VDD