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CA3338D 数据表(PDF) 6 Page - Intersil Corporation |
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CA3338D 数据表(HTML) 6 Page - Intersil Corporation |
6 / 7 page 10-16 Dynamic Characteristics Keeping the full-scale range (VREF+ - VREF-) as high as possible gives the best linearity and lowest “glitch” energy (referred to 1V). This provides the best “P” and “N” channel gate drives (hence saturation resistance) and propagation delays. The VREF+ (and VREF- if bipolar) terminal should be well bypassed as near the chip as possible. “Glitch” energy is defined as a spurious voltage that occurs as the output is changed from one voltage to another. In a binary input converter, it is usually highest at the most significant bit transition (7FHEX to 80HEX for an 8 bit device), and can be measured by displaying the output as the input code alter- nates around that point. The “glitch” energy is the area between the actual output display and an ideal one LSB step voltage (subtracting negative area from positive), at either the positive or negative-going step. It is usually expressed in pV/s. The CA3338 uses a modified R2R ladder, where the 3 most significant bits drive a bar graph decoder and 7 equally weighted resistors. This makes the “glitch” energy at each 1/8 scale transition (1FHEX to 20HEX, 3FHEX to 40HEX, etc.) essentially equal, and far less than the MSB transition would otherwise display. For the purpose of comparison to other converters, the output should be resistively divided to 1V full scale. Figure 5 shows a typical hook-up for checking “glitch” energy or settling time. The settling time of the A/D is mainly a function of the output resistance (approximately 160 Ω in parallel with the load resis- tance) and the load plus internal chip capacitance. Both “glitch” energy and settling time measurements require very good circuit and probe grounding: a probe tip connector such as Tektronix part number 131-0258-00 is recommended. 0 00 C B FROM “0” SCALE INTEGRAL LINEARITY ERROR (SHOWN -) STRAIGHT LINE TO FULL SCALE VOLTAGE INPUT CODE = IDEAL TRANSFER CURVE = ACTUAL TRANSFER CURVE A = IDEAL STEP SIZE (1/255 OF FULL B - A = +DIFFERENTIAL LINEARITY ERROR C - A = -DIFFERENTIAL LINEARITY ERROR A SCALE -“0” SCALE VOLTAGE) FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY ERROR CLOCK 8 DATA BITS +5V 15 16 14 8 1-7, 9 LE D0 - D7 VDD COMP VSS CA3338 VOUT VREF+ VEE 12 13 11 10 +5V +2.5V -2.5V R1 R2 PROBE TIP REMOTE VOUT R3 VREF- OR BNC CONNECTOR DIGITAL GROUND ANALOG GROUND + + + FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT FUNCTION CONNECTOR R1 R2 R3 VOUT (P-P) Oscilloscope Display Probe Tip 82 Ω 62 Ω N/C 1V Match 93 Ω Cable BNC 75 160 93 1V Match 75 Ω Cable BNC 18 130 75 1V Match 50 Ω Cable BNC Short 75 50 0 79V NOTES: 2. VOUT(P-P) is approximate, and will vary as ROUT of D/A varies. 3. All drawn capacitors are 0.1 µF multilayer ceramic/4.7µF tantalum. 4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation. CA3338, CA3338A |
类似零件编号 - CA3338D |
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类似说明 - CA3338D |
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