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CA3318CD 数据表(PDF) 8 Page - Intersil Corporation |
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CA3318CD 数据表(HTML) 8 Page - Intersil Corporation |
8 / 12 page 4-16 At the same time a second set of commutating capacitors and amplifiers is also auto-balanced. The balancing of the second-stage amplifier at its intrinsic trip point removes any tracking differences between the first and second amplifier stages. The cascaded auto-balance (CAB) technique, used here, increases comparator sensitivity and temperature tracking. In the “Sample Unknown” phase, all ladder tap switches and comparator shorting switches are opened. At the same time VlN is switched to the first set of commutating capacitors. Since the other end of the capacitors are now looking into an effectively open circuit, any input voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators that had tap voltages greater than VlN will go to a “high” state at their outputs. All comparators that had tap voltages lower than VlN will go to a “low” state. The status of all these comparator amplifiers is AC coupled through the second-stage comparator and stored at the end of this phase ( φ2) by a latching amplifier stage. The latch feeds a second latching stage, triggered at the end of φ1. This delay allows comparators extra settling time. The status of the comparators is decoded by a 256 to 9-bit decoder array, and the results are clocked into a storage register at the end of the next φ2. A 3-stage buffer is used at the output of the 9 storage regis- ters which are controlled by two chip-enable signals. CE1 will independently disable B1 through B6 when it is in a high state. CE2 will independently disable B1 through B8 and the OF buffers when it is in the low state. To facilitate usage of this device, a phase control input is pro- vided which can effectively complement the clock as it enters the chip. Continuous-Clock Operation One complete conversion cycle can be traced through the CA3318 via the following steps. (Refer to timing diagram.) With the phase control in a “low” state, the rising edge of the clock input will start a “sample” phase. During this entire “high” state of the clock, the comparators will track the input voltage and the first-stage latches will track the comparator outputs. At the falling edge of the clock, all 256 comparator outputs are captured by the 256 latches. This ends the “sam- ple” phase and starts the “auto-balance” phase for the com- parators. During this “low” state of the clock, the output of the latches settles and is captured by a second row of latches when the clock returns high. The second-stage latch output propagates through the decode array, and a 9-bit code appears at the D inputs of the output registers. On the next falling edge of the clock, this 9-bit code is shifted into the out- put registers and appears with time delay tD as valid data at the output of the three-state drivers. This also marks the end of the next “sample” phase, thereby repeating the conversion process for this next cycle. Pulse-Mode Operation The CA3318 needs two of the same polarity clock edges to complete a conversion cycle: If, for instance, a negative going clock edge ends sample “N”, then data “N” will appear after the next negative going edge. Because of this require- ment, and because there is a maximum sample time of 500ns (due to capacitor droop), most pulse or intermittent sample applications will require double clock pulsing. If an indefinite standby state is desired, standby should be in auto-balance, and the operation would be as in Figure 3A. If the standby state is known to last less than 500ns and lowest average power is desired, then operation could be as in Figure 3B. Increased Accuracy In most cases the accuracy of the CA3318 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, five adjustments can be made to obtain better accuracy, i.e., offset trim; gain trim; and 1/4, 1/ 2 and 3/ 4 point trim. Offset Trim In general, offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the op amp. When this is not possible the VREF- input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/2 LSB. The equa- tion is as follows: VlN (0 to 1 transition) = 1/ 2 LSB = 1/ 2 (VREF/256) = VREF/512. If VlN for the first transition is less than the theoretical, then a single-turn 50 Ω pot connected between VREF- and ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0-to-1 transition occurs. If VlN for the first transition is greater than the theoretical, then the 50 Ω pot should be connected between VREF- and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. Gain Trim In general, the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the op amp. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VlN should be set to the 255 to overflow transition. That voltage is 1/3 LSB less than VREF+ and is calculated as follows: VlN (255 to 256 transition) = VREF - VREF/512 = VREF(511/512). To perform the gain trim, first do the offset trim and then apply the required VlN for the 255 to overflow transition. Now adjust VREF+ until that transition occurs on the outputs. CA3318 |
类似零件编号 - CA3318CD |
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类似说明 - CA3318CD |
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