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CA3262A 数据表(PDF) 4 Page - Intersil Corporation |
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CA3262A 数据表(HTML) 4 Page - Intersil Corporation |
4 / 9 page 4 Applications Typical circuit configurations for applying the CA3262 and CA3262A are shown in the application circuit of Figure 2. To their rated capabilities, both circuits can be used to drive induc- tive, resistive and lamp loads. The CA3262A has a lower VSAT than the CA3262 and is rated for 125oC ambient temperature applications. The CA3262 data sheet rating is 85oC. Otherwise, the protection features described apply to both the CA3262 and CA3262A. The maximum voltage for full load current switching is the output sustaining voltage, VCE(SUS) which should not exceed 40V. To provide a means of over-voltage protection, on-chip steering diodes are connected from each output to one of two CLAMP pins. Over-voltage pulses may be generated from inductive load switching and must be clamped or limited to a peak voltage less than VCE(SUS). To limit an inductive voltage pulse, a zener diode should be connected to the appropriate CLAMP pin. When the voltage pulse exceeds the zener thresh- old, the excess energy is dumped to ground via the on-chip steering diode and the external zener diode. The on-chip diodes may be used in a free-wheeling mode by connecting the CLAMP pins to an external clamp supply voltage. Zener diode clamp protection is preferred over the power supply clamp option, primarily because the power supplies may be subject to large transient changes; including turn-ON and turn-OFF conditions where non-tracking conditions between supplies could allow forward conduction through the steering diodes. For all transient conditions of either method, the clamp voltage should greater than the maximum supply voltage of the switching outputs and less than VCE(SUS). Note that the rate of change of the output current during load switching is fast. Therefore, even small values of inductance, including the inductance of a few meters of hook-up wire to the load circuit, can generate voltage spikes of considerable amplitude at the output terminals and may require clamping to protect the device ratings. Current-limiting is provided as protection for shorted or over- loaded output conditions. Voltage is sampled across a small metal resistor in the emitter of each output stage. When the volt- age exceeds a preset comparator level, drive is reduced to the output. Current limiting is sustained unless thermal conditions exceed the preset thermal shutdown temperature of 155oC. If an output is shorted, the remaining three outputs will continue to function normally unless the continued heat spreading is sufficient to raise the junction temperature at any other output to a level greater than 155oC. High ambient tem- perature conditions may allow this to happen. The degree of interaction is minimized at chip layout design by separating the output devices, each to a separate corner of the chip. As noted, the thermal resistance values of the PDIP, PLCC and SOIC packages are improved by direct connection of the leads to the chip mounting pad. For a normal PC Board application, the thermal resistance coefficient for each pack- age can be significantly lowered by increasing ground cop- per area on the PC board next to the ground pins of the IC. Input Capacitance, Input CIN - - -- 3 - pF Enable Capacitance CEN - - - - 4.4 - pF NOTES: 1. The CA3262 and CA3262A have on-chip limiting for transient peak currents. Under short-circuit conditions with voltage applied to the collector of the output transistor and with the output transistor turned ON, the current will increase to 1.2A, typical. Over-Current Limiting protects a short circuit condition for a normal operating range of output supply voltage. During a short circuit condition, the output driver will shortly thereafter (approx. 5ms) go into Over-Temperature Limiting. While Over-Current Limiting may range to peak currents greater than 2A, each output will typically withstand a direct short circuit up to supply voltage levels of 16V. Excessive dissipation before thermal limiting occurs may cause dam- age to the chip for supply voltages greater than 18V. The CA3262 and CA3262A are rated to withstand peak current, cold turn-on conditions of #168 or #194 lamp loads. 2. The total DC current for the CA3262 and CA3262A with all 4 outputs ON should not exceed the total of (4 x 0.7A + Max. ICC) ~ 2.85A. This level of current will significantly increase the chip temperature due to increased dissipation and may cause thermal shutdown in high ambient tem- perature conditions (See Absolute Maximum Ratings for Dissipation). Any one output may be allowed to exceed 0.7A but may be subject to Over-Current Limiting above the ILIM min. limit of 0.7A. As a practical limit, no single output should be loaded to more than 1A (Max). 3. Normal applications require a surface mount of the 28 lead PLCC and 24 lead SOIC packages on a PC Board. The PLCC, SOIC and PDIP packages have power lead frame construction through the ground pins to conduct heat from the frame to the PC Board ground area. Thermal resistance, θ JA, is given for a surface mount of the 28 lead PLCC and the 24 lead SOIC packages on a 1 oz. copper PC board with minimal ground area and with 2 square inches of ground area. 4. ICC varies with temperature. Typically, ICC(ON) is 18mA at 125 oC and 41mA at -40oC. Typically, I CC(OFF) is 2.2mA at 125 oC and 1.2mA at -40oC. 5. Tested with a switched-off 500mA Load of 120mH (with 24 Ω series resistance), VBATT = 12V and the outputs (VCE) clamped to +40V maximum with an external zener diode. Electrical Specifications VCC = 5.5V, TA = -40 oC to 125oC for CA3262A and V CC = 5.5V, TA = -40 oC to 85oC for CA3262 Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS CA3262 CA3262A UNITS MIN TYP MAX MIN TYP MAX CA3262A, CA3262 |
类似零件编号 - CA3262A |
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类似说明 - CA3262A |
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