2

Absolute Maximum Ratings

Thermal Information

Operating Conditions

Thermal Resistance (Typical, Note 2)

θ

16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .

90

16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .

185

Maximum Power Dissipation (Any One Transistor) . . . . . . . . 85mW

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The collector of each transistor of these devices is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected

to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.

2.

Electrical Specifications

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DC CHARACTERISTICS FOR EACH TRANSISTOR

Collector to Base Breakdown Voltage

12

20

-

V

Collector to Emitter Breakdown Voltage

8

10

-

V

20

-

-

V

Emitter Cutoff Current (Note 3)

-

-

10

µA

Collector Cutoff Current

-

-

1

µA

Collector Cutoff Current

-

-

100

nA

DC Forward Current Transfer Ratio

-

110

-

40

150

-

-

150

-

Base to Emitter Voltage

0.62

0.71

0.82

V

Collector to Emitter Saturation Voltage

-

0.13

0.50

V

Base to Emitter Saturation Voltage

0.74

-

0.94

V

NOTE:

3. On small-geometry, high-frequency transistors, it is very good practice never to take the Emitter Base Junction into reverse breakdown. To do

electrostatic discharge and transients in the circuits in which they are used. Moreover, CMOS handling procedures should be employed.

CA3227