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CS82C37A 数据表(PDF) 11 Page - Intersil Corporation |
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CS82C37A 数据表(HTML) 11 Page - Intersil Corporation |
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11 / 23 page  4-202 82C37A Software Commands There are special software commands which can be executed by reading or writing to the 82C37A. These com- mands do not depend on the specific data pattern on the data bus, but are activated by the I/O operation itself. On read type commands, the data value is not guaranteed. These commands are: Clear First/Last Flip-Flop - This command is executed prior to writing or reading new address or word count infor- mation to the 82C37A. This command initializes the flip-flop to a known state (low byte first) so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. Set First/Last Flip-Flop - This command will set the flip-flop to select the high byte first on read and write operations to address and word count registers. Master Clear - This software instruction has the same effect as the hardware Reset. The Command, Status, Request, and Temporary registers, and Internal First/Last Flip-Flop and mode register counter are cleared and the Mask register is set. The 82C37A will enter the idle cycle. Clear Mask Register - This command clears the mask bits of all four channels, enabling them to accept DMA requests. Clear Mode Register Counter - Since only one address location is available for reading the Mode registers, an inter- nal two-bit counter has been included to select Mode regis- ters during read operation. To read the Mode registers, first execute the Clear Mode Register Counter command, then do consecutive reads until the desired channel is read. Read order is channel 0 first, channel 3 last. The lower two bits on all Mode registers will read as ones. External EOP Operation The EOP pin is a bidirectional, open drain pin which may be driven by external signals to terminate DMA operation. Because EOP is an open drain pin an external pull-up resis- tor to VCC is required. The value of the external pull-up resistor used should guarantee a rise time of less than 125ns. It is important to note that the 82C37A will not accept external EOP signals when it is in a SI (Idle) state. The controller must be active to latch EXT EOP. Once latched, the EXT EOP will be acted upon during the next S2 state, unless the 82C37A enters an idle state first. In the latter case, the latched EOP is cleared. External EOP pulses occurring between active DMA transfers in demand mode will not be recognized, since the 82C37A is in an SI state. CHANNEL REGISTER OPERATION SIGNALS FIRST/LAST FLIP-FLOP STATE DATA BUS DB0-DB7 CS IOR IOW A3A2A1A0 0 Base and Current Address Write 0100000 0 A0-A7 0100000 1 A8-A15 Current Address Read 0010000 0 A0-A7 0010000 1 A8-A15 Base and Current Word Count Write 0100001 0 W0-W7 0100001 1 W8-W15 Current Word Count Read 0010001 0 W0-W7 0010001 1 W8-W15 1 Base and Current Address Write 0100010 0 A0-A7 0100010 1 A8-A15 Current Address Read 0010010 0 A0-A7 0010010 1 A8-A15 Base and Current Word Count Write 0100011 0 W0-W7 0100011 1 W8-W15 Current Word Count Read 0010011 0 W0-W7 0010011 1 W8-W15 2 Base and Current Address Write 0100100 0 A0-A7 0100100 1 A8-A15 Current Address Read 0010100 0 A0-A7 0010100 1 A8-A15 Base and Current Word Count Write 0100101 0 W0-W7 0100101 1 W8-W15 Current Word Count Read 0010101 0 W0-W7 0010101 1 W8-W15 3 Base and Current Address Write 0100110 0 A0-A7 0100110 1 A8-A15 Current Address Read 00101100 A0-A7 00101101 A8-A15 Base and Current Word Count Write 01001110 W0-W7 01001111 W8-W15 Current Word Count Read 00101110 W0-W7 00101111 W8-W15 FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES |
类似零件编号 - CS82C37A |
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类似说明 - CS82C37A |
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