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M82380 数据表(PDF) 6 Page - Intel Corporation

部件名 M82380
功能描述  HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
Download  134 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

M82380 数据表(HTML) 6 Page - Intel Corporation

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M82380
10 FUNCTIONAL OVERVIEW
The M82380 contains several independent function-
al modules The following is a brief discussion of the
components and features of the M82380 Each
module has a corresponding detailed section later in
this data sheet Those sections should be referred
to for design and programming information
11 M82380 Architecture
The M82380 is comprised of several computer sys-
tem functions that are normally found in separate
LSI and VLSI components These include a high-
performance eight-channel 32-bit Direct Memory
Access Controller a 20-level Programmable Inter-
rupt Controller which is a superset of the M8259A
four 16-bit Programmable Interval Timers which are
functionally equivalent to the M82C54 timers a
DRAM Refresh Controller a Programmable Wait
State Generator and system reset logic The inter-
face to the M82380 is optimized for high-perform-
ance operation with the i386 microprocessor
The M82380 operates directly on the i386 micro-
processor bus In the Slave Mode it monitors the
state of the processor at all times and acts or idles
according to the commands of the host It monitors
the address pipeline status and generates the pro-
grammed number of wait states for the device being
accessed The M82380 also has logic to reset the
i386 microprocessor via hardware or software reset
requests and processor shutdown status
After a system reset the M82380 is in the Slave
Mode It appears to the system as an IO device It
becomes a bus master when it is performing DMA
transfers
To maintain compatibility with existing software the
registers within the M82380 are accessed as bytes
If the internal logic of the M82380 requires a delay
before another access by the processor wait states
are automatically inserted into the access cycle
This allows the programmer to write initialization rou-
tines
etc
without regard to hardware recovery
times
Figure 1 shows the basic architectural components
of the M82380 The following sections briefly dis-
cuss the architecture and function of each of the
distinct sections of the M82380
271070 – 2
Figure 1 Architecture of the M82380
6


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