M82380 datasheet(36/134 Pages) INTEL

部件名	M82380

功能描述	HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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M82380

the bus even if DREQn goes inactive before the

transfer is complete In the Single Mode the control-

ler will execute single data transfers relinquishing

the bus between each transfer as long as DREQn is

active

Normal termination of a DMA process due to expira-

tion of the byte count (Terminal Count-TC) is shown

in Figure 29 The condition of DREQn is ignored until

after the process is terminated If the channel is pro-

grammed to auto-initialize HOLD will be held active

for an additional seven clock cycles while the auto-

initialization takes place

Table 6 shows the DMA channel activity due to EOP

or Byte Count expiring (Terminal Count)

Table 6 DMA Channel Activity Due to Terminal Count or External EOP

Single

Auto-

Chaining-

Buffer Process

or Chaining-

Initialize

Base Loaded

Base Empty

Event

Terminal Count

True

X

True

X

True

X

EOP Input

X

0

X

0

X

0

Results

Current Registers

Load

Channel Mask

Set

EOP Output

0

X

0

X

1

X

Terminal Count Status

Set

Software Request

CLR

271070 – 28

Figure 29 Termination of a DMA Process Due to Expiration of Current Byte Count

36

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