M82380 datasheet(35/134 Pages) INTEL

部件名	M82380

功能描述	HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

Download	134 Pages

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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35 / 134 page

M82380

When the M82380 DMA Controller is finished with its

current bus activity it returns control of the bus to

the host processor This is done by driving the

HOLD signal inactive The M82380 does not drive

any address or data bus signals after HOLD goes

low It enters the Slave Mode until another DMA pro-

cess is requested The processor acknowledges

that it has regained control of the bus by forcing the

HLDA signal inactive Note that the M82380’s DMA

Controller will not re-request control of the bus until

the entire HOLDHLDA handshake sequence is

complete

The M82380 DMA Controller will terminate a current

DMA process for one of three reasons expired byte

count end-of-process command (EOP activated)

from a peripheral or de-activated DMA request sig-

nal In each case the controller will de-assert HOLD

immediately after completing the data transfer in

progress These three methods of process termina-

tion are illustrated in Figures 29 32 and 31 respec-

tively

An expired byte count indicates that the current pro-

cess is complete as programmed and the channel

has no further transfers to process The channel

must be restarted according to the currently pro-

grammed Buffer Transfer Mode or reprogrammed

completely including a new Buffer Transfer Mode

If the peripheral activates the EOP signal it is indi-

cating that it will not accept or deliver any more data

for the current buffer The M82380 DMA Controller

considers this as a completion of the channel’s cur-

rent process and interprets the condition the same

way as if the byte count expired

The action taken by the M82380 DMA Controller in

response to a de-activated DREQn signal depends

on the Data Transfer Mode of the channel In the

Demand Mode data transfers will take place as long

as the DREQn is active and the byte count has not

expired In the Block Mode the controller will com-

plete the entire block transfer without relinquishing

271070 – 27

NOTE

Channel priority resolution takes place during the bus state before HLDA is asserted allowing the DMA Controller to

respond to HLDA without extra idle bus states

Figure 28 Beginning of a DMA Process

35

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