M82380 datasheet(34/134 Pages) INTEL

部件名	M82380

功能描述	HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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M82380

DATA PATH WIDTH AND DATA TRANSFER

RATE CONSIDERATIONS

The number of bus cycles used to transfer a single

‘word’ of data is affected by whether the Two-Cycle

or the Fly-By (Single-Cycle) transfer method is used

The number of bus cycles used to transfer data di-

rectly affects the data transfer rate Inefficient use of

bus cycles will decrease the effective data transfer

rate that can be obtained Generally the data trans-

fer rate is halved by using Two-Cycle transfers in-

stead of Fly-By transfers

The choice of data path widths of both Target and

Requester affects the data transfer rate also During

each bus cycle the largest pieces of data possible

should be transferred

The data path width of the devices to be accessed

must be programmed into the DMA controller The

M82380 defaults after reset to 8-bit-to-8-bit data

transfers but the Target and Requester can have

different data path widths independent of each oth-

er and independent of the other channels Since this

is a software programmable function more discus-

sion of the uses of this feature are found in the sec-

tion on programming

READ WRITE AND VERIFY CYCLES

Three different bus cycle types may be used in a

data transfer They are the Read Write and Verify

cycles These cycle types dictate the way in which

the M82380 operates on the data to be transferred

A Read Cycle transfers data from the Target to the

Requester A Write Cycle transfers data from the

Requester to the target In a Fly-By transfer the ad-

dress and bus status signals indicate the access

(read or write) to the Target the access to the Re-

quester is assumed to be the opposite

The Verify Cycle is used to perform a data read only

No write access is indicated or assumed in a Verify

Cycle The Verify Cycle is useful for validating block

fill operations An external comparator must be pro-

vided to do any comparisons on the data read

34 Bus Arbitration and Handshaking

Figure 27 shows the flow of events in the DMA re-

quest arbitration process The arbitration sequence

starts when the Requester asserts a DREQn (or

DMA service is requested by software) Figure 28

shows the timing of the sequence of events follow-

ing a DMA request This sequence is executed for

each channel that is activated The DREQn signal

can be replaced by a software DMA channel request

with no change in the sequence

271070 – 26

Figure 27 Bus Arbitration and DMA Sequence

After the Requester asserts the service request the

M82380 will request control of the bus via the HOLD

signal The M82380 will always assert the HOLD sig-

nal one bus state after the service request is assert-

ed The i386 processor responds by asserting the

HLDA signal thus releasing control of the bus to the

M82380 DMA Controller

Priority of pending DMA service requests is arbitrat-

ed during the first state after HLDA is asserted by

the i386 processor The next state will be the begin-

ning of the first transfer access of the highest priority

process

34

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