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M82380 数据表(PDF) 2 Page - Intel Corporation

部件名 M82380
功能描述  HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
Download  134 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

M82380 数据表(HTML) 2 Page - Intel Corporation

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M82380
M82380
HIGH PERFORMANCE 32-BIT DMA CONTROLLER
WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
CONTENTS
PAGE
10 FUNCTIONAL OVERVIEW
6
11 M82380 Architecture
6
111 DMA Controller
7
112 Programmable Interval Timers
8
113 Interrupt Controller
9
114 Wait State Generator
10
115 DRAM Refresh Controller
10
116 CPU Reset Function
11
117 Register Map Relocation
11
12 Host Interface
11
20 i386TM PROCESSOR HOST INTERFACE
12
21 Master and Slave Modes
13
22 M80386 Interface Signals
13
221 Clock (CLK2)
13
222 Data Bus (D0 – D31)
13
223 Address Bus (A31 – A2)
14
224 Byte Enable (BE3 – BE0)
14
225 Bus Cycle Definition Signals (DC WR MIO)
15
226 Address Status (ADS)
15
227 Transfer Acknowledge (READY)
15
228 Next Address Request (NA)
15
229 Reset (RESET CPURST)
15
2210 Interrupt Out (INT)
17
23 M82380 Bus Timing
17
231 Address Pipelining
17
232 Master Mode Bus Timing
17
233 Slave Mode Bus Timing
20
30 DMA CONTROLLER
21
31 Functional Description
22
32 Interface Signals
23
321 DREQn and EDACK (0 – 2)
24
322 HOLD and HLDA
24
323 EOP
24
33 Modes of Operation
24
331 TargetRequester Definition
25
332 Buffer Transfer Processes
25
333 Data Transfer Modes
26
334 Channel Priority Arbitration
30
335 Combining Priority Modes
32
336 Bus Operation
33
34 Bus Arbitration and Handshaking
34
341 Synchronous and Asynchronous Sampling of DREQn and EOP
37
342 Arbitration of Cascaded Master Requests
39
343 Arbitration of Refresh Requests
41
2


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