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AD5532 数据表(PDF) 7 Page - Analog Devices |
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AD5532 数据表(HTML) 7 Page - Analog Devices |
7 / 20 page AD5532 Rev. D | Page 7 of 20 SERIAL INTERFACE Table 4. Parameter1, 2 Limit at TMIN, TMAX (A Version) Unit Conditions/Comments fCLKIN3 14 MHz max SCLK frequency t1 28 ns min SCLK high pulse width t2 28 ns min SCLK low pulse width SYNC falling edge to SCLK falling edge setup time t3 15 ns min SYNC low time t4 50 ns min t5 10 ns min DIN setup time t6 5 ns min DIN hold time SYNC falling edge to SCLK rising edge setup time for read back t7 5 ns min t84 20 ns max SCLK rising edge to DOUT valid t94 60 ns max SCLK falling edge to DOUT high impedance 10th SCLK falling edge to SYNC falling edge for read back t10 400 ns min 24th SCLK falling edge to SYNC falling edge for DAC mode write t11 400 ns min SCLK falling edge to SYNC falling edge setup time for read back t125 7 ns min t1 t3 t2 MSB LSB SCLK 123456789 10 SYNC DIN t4 t5 t6 Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes) SCLK 12345 21 22 23 24 1 DIN SYNC t1 t3 t2 t4 t5 t6 LSB MSB t11 Figure 5. 24-Bit Write (DAC Mode) SCLK 10 12 34567 89 10 11 12 13 14 MSB LSB DOUT SYNC t7 t1 t2 t12 t4 t8 t10 t9 Figure 6. 14-Bit Read (Both Readback Modes) 1 See Figure 4, Figure 5, and Figure 6. 2 Guaranteed by design and characterization, not production tested. 3 In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns. 4 These numbers are measured with the load circuit of Figure 3. 5 SYNC should be taken low while SCLK is low for read back. |
类似零件编号 - AD5532_15 |
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类似说明 - AD5532_15 |
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