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FW82371 数据表(PDF) 95 Page - Intel Corporation |
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FW82371 数据表(HTML) 95 Page - Intel Corporation |
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95 / 284 page  82371AB (PIIX4) 95 4/9/97 2:23 PM PIIX4aDS INTEL CONFIDENTIAL (until publication date) PRELIMINARY 5.1.11. SIDETIM—SLAVE IDE TIMING REGISTER (FUNCTION 1) Address Offset: 44h Default Value: 00h Attribute: Read/Write Only This register controls PIIX4’s IDE interface and selects the timing characteristics for the slave drives on each IDE channel. This allows for programming of independent operating modes for each IDE agent. This register has no affect unless the SITRE bit is enabled in the IDETIM Register. See Table 14 for programming values for various PIO Timing Modes. Bit Description 7:6 Secondary Drive 1 IORDY Sample Point (SISP1). This field selects the number of PCI clocks between SDIOx# assertion and the first SIORDY sample point for the slave drive on the secondary channel. Bits[7:6] Number Of Clocks 00 5 01 4 10 3 11 2 5:4 Secondary Drive 1 Recovery Time (SRTC1). This field selects the minimum number of PCI clocks between the last SIORDY# sample point and the SDIOx# strobe of the next cycle for the slave drive on the secondary channel. Bits[5:4] Number Of Clocks 00 4 01 3 10 2 11 1 3:2 Primary Drive 1 IORDY Sample Point (PISP1). This field selects the number of PCI clocks between PDIOx# assertion and the first PIORDY sample point for the slave drive on the primary channel. Bits[3:2] Number Of Clocks 00 5 01 4 10 3 11 2 1:0 Primary Drive 1 Recovery Time (PRTC1). This field selects the minimum number of PCI clocks between the last PIORDY# sample point and the PDIOx# strobe of the next cycle for the slave drive on the primary channel. Bits[1:0] Number Of Clocks 00 4 01 3 10 2 11 1 |
类似零件编号 - FW82371 |
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类似说明 - FW82371 |
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