DA28F640J5-150 datasheet(31/53 Pages) INTEL

部件名	DA28F640J5-150

功能描述	StrataFlash MEMORY TECHNOLOGY 32 AND 64 MBIT

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制造商	INTEL [Intel Corporation]

网页	http://www.intel.com

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INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT

31

ADVANCE INFORMATION

Table 15. Configuration Coding Definitions

Reserved

Pulse On

Program

Complete(1)

Pulse On

Erase

Complete(1)

bits 7–2

bit 1

bit 0

DQ7–DQ2 =

Reserved

DQ1–DQ0 =

STS Pin Configuration Codes

00 =

default, level mode RY/BY#

(device ready) indication

01 =

pulse on Erase complete

10 =

pulse on Program complete

11 =

pulse on Erase or Program Complete

Configuration Codes 01b, 10b, and 11b are all pulse

mode such that the STS pin pulses low then high

when the operation indicated by the given

configuration is completed.

Configuration Command Sequences for STS pin

configuration (masking bits DQ7–DQ2 to 00h) are

as follows:

Default RY/BY# level mode:

B8h, 00h

ER INT (Erase Interrupt):

B8h, 01h

Pulse-on-Erase Complete

PR INT (Program Interrupt):

B8h, 02h

Pulse-on-Program Complete

ER/PR INT (Erase or Program Interrupt):

B8h, 03h

Pulse-on-Erase or Program Complete

DQ7–DQ2 are reserved for future use.

default (DQ1–DQ0 = 00)

RY/BY#, level mode

— used to control HOLD to a memory controller to

prevent accessing a flash memory subsystem while

any flash device's WSM is busy.

configuration 01

ER INT, pulse mode

— used to generate a system interrupt pulse when

any flash device in an array has completed a Block

Erase or sequence of Queued Block Erases. Helpful

for reformatting blocks after file system free space

reclamation or “cleanup”

configuration 10

PR INT, pulse mode

— used to generate a system interrupt pulse when

any flash device in an array has complete a Program

operation. Provides highest performance for servicing

continuous buffer write operations.

configuration 11

ER/PR INT, pulse mode

— used to generate system interrupts to trigger

servicing of flash arrays when either erase or

program operations are completed when a common

interrupt service routine is desired.

NOTE:

1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.

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Intel Corporation	DA28F640J5-150	617Kb / 51P	5 Volt Intel StrataFlash짰 Memory

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