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DA28F016XS15 数据表(PDF) 18 Page - Intel Corporation

部件名 DA28F016XS15
功能描述  16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

DA28F016XS15 数据表(HTML) 18 Page - Intel Corporation

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28F016XS FLASH MEMORY
E
18
4.3
28F008SA—Compatible Mode Command Bus Definitions
First Bus Cycle
Second Bus Cycle
Command
Notes
Oper
Addr
Data
(4)
Oper
Addr
Data
(4)
Read Array
Write
X
xxFFH
Read
AA
AD
Intelligent Identifier
1
Write
X
xx90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
xx70H
Read
X
CSRD
Clear Status Register
3
Write
X
xx50H
Program
Write
X
xx40H
Write
PA
PD
Alternate Program
Write
X
xx10H
Write
PA
PD
Block Erase/Confirm
Write
X
xx20H
Write
BA
xxD0H
Erase Suspend/Resume
Write
X
xxB0H
Write
X
xxD0H
ADDRESS
DATA
AA = Array Address
AD = Array Data
BA = Block Address
CSRD = CSR Data
IA = Identifier Address
ID = Identifier Data
PA = Program Address
PD = Program Data
X = Don’t Care
NOTES:
1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters data program, erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register
definitions.
4. The upper byte of the data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.


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